dadda-multiplier

Here are 5 public repositories matching this topic...

tharunchitipolu / Dadda-Multiplier-using-CSA

Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.

rtl verilog fulladder vlsi multiplier hardware-description-language wallace vlsi-design vlsi-project dadda-tree carry-save-adder fast-multiplication dadda-multiplier tree-multipliers

Updated Jun 6, 2024
Verilog

rohankalbag / vlsi-design

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VLSI Design - Autumn Semester 2022 - Indian Institute of Technology Bombay

vhdl ngspice digital-logic-design brent-kung vlsi-design multiply-accumulate dadda-multiplier

Updated May 10, 2023
VHDL

sakthisamita / Multipliers

Star

wallace-tree-multiplier dadda-multiplier

Updated Nov 1, 2025
Verilog

VLSI-Shubh / Delay-and-Power-Analysis-of-a-Static-8x8-Dadda-Multiplier-Circuit

Star

High-speed 8×8 Dadda multiplier designed in 45nm CMOS technology with hybrid transmission gate/CMOS logic. Features 4:2 compressor-based partial product reduction, critical path delay of 0.204ns, and comprehensive delay & power analysis.

vlsi-physical-design dadda-multiplier delay-analysis cmos-logic arithematic-circuits

Updated Mar 10, 2025

Sarkar22 / sv-arith

Star

Parametric structural adders and multipliers in SystemVerilog: unsigned, signed (Baugh-Wooley and radix-4 Booth) and floating point (FP8 e4m3/e5m2, bf16, fp16), verified exhaustively and placed and routed on sky130 (41-design area-delay sweep)

Updated Sep 20, 2026
SystemVerilog

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