PolarFire SoC M-Mode Support with SC QSPI Flash

.gdbinit

@@ -1,7 +1,9 @@
 file wolfboot.elf
 tar rem:3333
-add-symbol-file test-app/image.elf
+add-symbol-file ../hart-software-services/build/hss-l2scratch.elf
 set pagination off
 foc c
 
-
+set $target_riscv=1
+set mem inaccessible-by-default off
+set architecture riscv:rv64

.github/workflows/test-configs.yml

@@ -272,9 +272,16 @@ jobs:
     with:
       arch: riscv64
       config-file: ./config/examples/polarfire_mpfs250.config
-      # Only building wolfBoot - not test app for now (cross compiler cannot find suitable multilib set for '-march=rv64imafd_zicsr_zmmul_zaamo_zalrsc'/'-mabi=lp64d')
-      # Consider building cached RISCV64 toolchain for this target
-      make-args: wolfboot.bin
+  microchip_mpfs250_qspi_test:
+    uses: ./.github/workflows/test-build-riscv.yml
+    with:
+      arch: riscv64
+      config-file: ./config/examples/polarfire_mpfs250_qspi.config
+  microchip_mpfs250_m_qspi_test:
+    uses: ./.github/workflows/test-build-riscv.yml
+    with:
+      arch: riscv64
+      config-file: ./config/examples/polarfire_mpfs250_m_qspi.config
 
   raspi3_test:
     uses: ./.github/workflows/test-build.yml

arch.mk

@@ -581,7 +581,17 @@ endif
 ## RISCV64 (64-bit)
 ifeq ($(ARCH),RISCV64)
   CROSS_COMPILE?=riscv64-unknown-elf-
-  CFLAGS+=-DMMU -DWOLFBOOT_DUALBOOT
+
+  # M-mode vs S-mode configuration
+  ifeq ($(RISCV_MMODE),1)
+    # Machine Mode: Running directly from eNVM/L2 SRAM
+    CFLAGS+=-DWOLFBOOT_RISCV_MMODE -DWOLFBOOT_DUALBOOT
+    # Use M-mode specific linker script
+    LSCRIPT_IN:=hal/$(TARGET)-m.ld
+  else
+    # Supervisor Mode (default): Running under HSS with DDR available
+    CFLAGS+=-DMMU -DWOLFBOOT_DUALBOOT
+  endif
 
   # If SD card or eMMC is enabled use update_disk loader with GPT support
   ifneq ($(filter 1,$(DISK_SDCARD) $(DISK_EMMC)),)
@@ -595,7 +605,17 @@ ifeq ($(ARCH),RISCV64)
     UPDATE_OBJS?=src/update_ram.o
   endif
 
-  ARCH_FLAGS=-march=rv64imafd -mabi=lp64d -mcmodel=medany
+  ifeq ($(RISCV_MMODE),1)
+    # E51 core: rv64imac (no FPU, no crypto extensions)
+    ARCH_FLAGS=-march=rv64imac -mabi=lp64 -mcmodel=medany
+  else
+    # U54 cores: rv64gc (with FPU)
+    ARCH_FLAGS=-march=rv64imafd -mabi=lp64d -mcmodel=medany
+
+    # FDT support required
+    CFLAGS+=-DWOLFBOOT_FDT
+    OBJS+=src/fdt.o
+  endif
   CFLAGS+=-fno-builtin-printf -DUSE_M_TIME -g -nostartfiles -DARCH_RISCV -DARCH_RISCV64
   CFLAGS+=$(ARCH_FLAGS)
   LDFLAGS+=$(ARCH_FLAGS)
@@ -607,9 +627,6 @@ ifeq ($(ARCH),RISCV64)
   # Unified RISC-V boot code (32/64-bit via __riscv_xlen)
   OBJS+=src/boot_riscv_start.o src/boot_riscv.o src/vector_riscv.o
 
-  CFLAGS+=-DWOLFBOOT_FDT
-  OBJS+=src/fdt.o
-
   ifeq ($(SPMATH),1)
     MATH_OBJS += $(WOLFBOOT_LIB_WOLFSSL)/wolfcrypt/src/sp_c64.o
   endif
@@ -1620,6 +1637,13 @@ ifeq ($(DEBUG_UART),1)
   endif
 endif
 
+# UART QSPI programmer (PolarFire SoC MPFS): receive binary over UART and
+# write it directly to QSPI flash. Requires EXT_FLASH=1 and DEBUG_UART=1.
+# Use tools/scripts/mpfs_qspi_prog.py on the host side.
+ifeq ($(UART_QSPI_PROGRAM),1)
+  CFLAGS+=-DUART_QSPI_PROGRAM
+endif
+
 ifeq ($(NXP_CUSTOM_DCD),1)
   CFLAGS+=-DNXP_CUSTOM_DCD
   OBJS+=$(NXP_CUSTOM_DCD_OBJS)

config/examples/polarfire_mpfs250.config

@@ -67,7 +67,7 @@ CFLAGS_EXTRA+=-DBOOT_PART_B=2
 # Speed up disk partition read (512KB chunks - max DMA size)
 CFLAGS_EXTRA+=-DDISK_BLOCK_SIZE=0x80000
 
-# DTS (Device Tree)
+# DTS (Device Tree) load address
 WOLFBOOT_LOAD_DTS_ADDRESS?=0x8A000000
 
 # Optional Encryption
@@ -77,7 +77,7 @@ WOLFBOOT_LOAD_DTS_ADDRESS?=0x8A000000
 #OBJS_EXTRA=src/my_custom_encrypt_key.o
 
 # Optional EMMC_SD debugging logs
-#CFLAGS_EXTRA+=-DDEBUG_MMC
+#CFLAGS_EXTRA+=-DDEBUG_SDHCI
 # Optional disk debugging logs
 #CFLAGS_EXTRA+=-DDEBUG_DISK
 #CFLAGS_EXTRA+=-DDISK_TEST

config/examples/polarfire_mpfs250_m_qspi.config

@@ -0,0 +1,112 @@
+# PolarFire SoC MPFS250T M-Mode (Machine Mode) with SC QSPI Flash
+#
+# This configuration runs wolfBoot directly from eNVM in M-mode (Machine Mode),
+# and boots a test application from SC QSPI flash to on-chip LIM (no DDR).
+#
+# Boot flow:
+#   1. eNVM (0x20220100) -> L2_SCRATCH (0x0A000000) - wolfBoot starts
+#   2. Load signed app image from SC QSPI flash to L2_SCRATCH (0x0A010200)
+#   3. Verify signature and boot
+#
+# Flash using mpfsBootmodeProgrammer (bootmode 1):
+#   java -jar mpfsBootmodeProgrammer.jar --bootmode 1 --die MPFS250T \
+#        --package FCG1152 --workdir $PWD wolfboot.elf
+
+ARCH?=RISCV64
+TARGET?=mpfs250
+SIGN?=ECC384
+HASH?=SHA384
+IMAGE_HEADER_SIZE=512
+WOLFBOOT_VERSION?=1
+ARMORED?=0
+DEBUG?=0
+DEBUG_SYMBOLS?=1
+DEBUG_UART?=1
+VTOR?=1
+NO_XIP?=1
+NVM_FLASH_WRITEONCE?=0
+UART_FLASH?=0
+V?=0
+NO_MPU?=1
+RAM_CODE?=0
+SPMATH?=0
+SPMATHALL?=1
+DUALBANK_SWAP?=0
+PKA?=0
+ENCRYPT=0
+WOLFTPM?=0
+ELF?=1
+#DEBUG_ELF?=1
+
+OPTIMIZATION_LEVEL=1
+
+# M-Mode Configuration
+# Runs on E51 core in Machine Mode from L2 SRAM
+RISCV_MMODE?=1
+
+# Stack size per hart (reduced for L2 SRAM constraints)
+CFLAGS_EXTRA+=-DSTACK_SIZE_PER_HART=8192
+
+# E51 core lacks RISC-V crypto extensions (Zknh), use portable C implementations
+NO_ASM?=1
+
+# QSPI Flash Configuration
+# Using Micron MT25QL01GBBB (128MB, 64KB sectors)
+EXT_FLASH?=1
+SPI_FLASH?=0
+
+# SPI Flash Controller Selection:
+# MPFS_SC_SPI: Use SC QSPI Controller (0x37020100) for fabric-connected flash.
+#              Direct register access to System Controller's QSPI instance.
+# DEFAULT:     Use MSS QSPI Controller (0x21000000) for external flash
+#              on MSS QSPI pins.
+CFLAGS_EXTRA+=-DMPFS_SC_SPI
+
+# No SD card or eMMC
+DISK_SDCARD?=0
+DISK_EMMC?=0
+
+# L2 SRAM Address for wolfBoot (256KB available)
+# Stack grows down from end of L2_SCRATCH
+WOLFBOOT_ORIGIN?=0x0A000000
+
+# Load application to L2 Scratchpad (above wolfBoot code, below stack)
+# wolfBoot occupies ~40KB at 0x0A000000, stack is 64KB at top of 256KB.
+# Note: update_ram places header at (LOAD_ADDRESS - IMAGE_HEADER_SIZE),
+# so offset by header size to keep header aligned.
+# IMPORTANT: Strip debug symbols from test-app ELF before signing to keep
+# the image small enough to fit in L2 Scratchpad (~150KB available).
+WOLFBOOT_LOAD_ADDRESS?=0x0A010200
+
+# Flash geometry (64 KB sector to match QSPI flash)
+WOLFBOOT_SECTOR_SIZE?=0x10000
+
+# Partition layout for 128MB QSPI flash
+# Boot partition:     0x00020000 - 0x01FFFFFF (~32MB)
+# Update partition:   0x02000000 - 0x03FFFFFF (~32MB)
+# Swap partition:     0x04000000 - 0x0400FFFF (64KB)
+WOLFBOOT_PARTITION_SIZE?=0x1FE0000
+WOLFBOOT_PARTITION_BOOT_ADDRESS?=0x20000
+WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x2000000
+WOLFBOOT_PARTITION_SWAP_ADDRESS?=0x4000000
+
+# Speed up reads from flash by using larger blocks
+CFLAGS_EXTRA+=-DWOLFBOOT_SHA_BLOCK_SIZE=4096
+
+# Debug options (useful for initial M-mode bring-up)
+#CFLAGS_EXTRA+=-DDEBUG_BOOT
+
+# Optional QSPI debugging
+# Uncomment for verbose QSPI debug output
+#CFLAGS_EXTRA+=-DDEBUG_QSPI
+
+# Optional QSPI flash test (erase/write/read on update partition)
+# Uncomment to run test during hal_init()
+#CFLAGS_EXTRA+=-DTEST_EXT_FLASH
+
+# UART QSPI programmer (disabled by default)
+# When enabled, wolfBoot prompts on UART at startup to receive a signed firmware
+# image and write it to QSPI flash -- no Libero/JTAG tool required for updates.
+# Use: python3 tools/scripts/mpfs_qspi_prog.py <port> <image.bin> [qspi_offset]
+# Requires EXT_FLASH=1 (already set) and DEBUG_UART=1.
+UART_QSPI_PROGRAM?=0