add bufif0 and rpmos

src/Language/SystemVerilog/AST/ModuleItem.hs

@@ -114,18 +114,22 @@ instance Show AlwaysKW where
 
 data NInputGateKW
     = GateAnd
+    | GateBufif0
     | GateNand
     | GateOr
     | GateNor
+    | GateRpmos
     | GateXor
     | GateXnor
     deriving Eq
 
 instance Show NInputGateKW where
     show GateAnd  = "and"
+    show GateBufif0  = "bufif0"
     show GateNand = "nand"
     show GateOr   = "or"
     show GateNor  = "nor"
+    show GateRpmos  = "rpmos"
     show GateXor  = "xor"
     show GateXnor = "xnor"
 

src/Language/SystemVerilog/Parser/Parse.y

@@ -873,9 +873,11 @@ OptGateName :: { (Identifier, [Range]) }
 
 NInputGateKW :: { NInputGateKW }
   : "and"  { GateAnd  }
+  | "bufif0" { GateBufif0 }
   | "nand" { GateNand }
   | "or"   { GateOr   }
   | "nor"  { GateNor  }
+  | "rpmos" { GateRpmos }
   | "xor"  { GateXor  }
   | "xnor" { GateXnor }
 NOutputGateKW :: { NOutputGateKW }

test/basic/gate.sv

@@ -6,11 +6,15 @@ module top;
     wire output_and_delay;
     wire output_not;
     wire output_buf_delay;
+    wire output_bufif0_delay;
+    wire output_rpmos;
 
     and (output_and, input_a, input_b);
     and #1 (output_and_delay, input_a, input_b);
     not (output_not, input_a);
     buf #2 foo_name (output_buf_delay, input_a);
+    bufif0 (output_bufif0_delay, input_a, input_b);
+    rpmos (output_rpmos, input_a, input_b);
 
     wire output_nand, output_or, output_nor, output_xor, output_xnor;
     nand (output_nand, input_a, input_b);
@@ -23,7 +27,7 @@ module top;
         $monitor("%3d ", $time,
             input_a, input_b,
             output_and, output_and_delay,
-            output_not, output_buf_delay,
+            output_not, output_buf_delay, output_bufif0_delay,
             output_nand, output_or, output_nor, output_xor, output_xnor);
 
         #1;