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Fix: Issue of SCB_DisableDCache(),SCB_InvalidateDCache(),SCB_CleanDCache() functions when compiling with -O0 #1350

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Fix: Issue of SCB_DisableDCache(),SCB_InvalidateDCache(),SCB_CleanDCache() functions when compiling with -O0 #1350

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e9bbf5a
Fix: Infinite while-loop issue in SCB_DisableDCache(), SCB_Invalidate…
devcoons Oct 25, 2021
0efc88c
update fileheader date to '25. October 2021'
devcoons Oct 25, 2021
66982bc
update fileheader version
devcoons Oct 26, 2021
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28 changes: 14 additions & 14 deletions CMSIS/Core/Include/cachel1_armv7.h
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Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
/******************************************************************************
* @file cachel1_armv7.h
* @brief CMSIS Level 1 Cache API for Armv7-M and later
* @version V1.0.1
* @date 19. April 2021
* @version V1.0.2
* @date 26. October 2021
******************************************************************************/
/*
* Copyright (c) 2020-2021 Arm Limited. All rights reserved.
Expand Down Expand Up @@ -181,9 +181,9 @@ __STATIC_FORCEINLINE void SCB_EnableDCache (void)
__STATIC_FORCEINLINE void SCB_DisableDCache (void)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
uint32_t ccsidr;
uint32_t sets;
uint32_t ways;
register uint32_t ccsidr;
register uint32_t sets;
register uint32_t ways;

SCB->CSSELR = 0U; /* select Level 1 data cache */
__DSB();
Expand Down Expand Up @@ -219,9 +219,9 @@ __STATIC_FORCEINLINE void SCB_DisableDCache (void)
__STATIC_FORCEINLINE void SCB_InvalidateDCache (void)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
uint32_t ccsidr;
uint32_t sets;
uint32_t ways;
register uint32_t ccsidr;
register uint32_t sets;
register uint32_t ways;

SCB->CSSELR = 0U; /* select Level 1 data cache */
__DSB();
Expand Down Expand Up @@ -254,9 +254,9 @@ __STATIC_FORCEINLINE void SCB_InvalidateDCache (void)
__STATIC_FORCEINLINE void SCB_CleanDCache (void)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
uint32_t ccsidr;
uint32_t sets;
uint32_t ways;
register uint32_t ccsidr;
register uint32_t sets;
register uint32_t ways;

SCB->CSSELR = 0U; /* select Level 1 data cache */
__DSB();
Expand Down Expand Up @@ -289,9 +289,9 @@ __STATIC_FORCEINLINE void SCB_CleanDCache (void)
__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
uint32_t ccsidr;
uint32_t sets;
uint32_t ways;
register uint32_t ccsidr;
register uint32_t sets;
register uint32_t ways;

SCB->CSSELR = 0U; /* select Level 1 data cache */
__DSB();
Expand Down