Refactor CMSIS Includes

CMSIS/Core/Include/cachel1_armv7.h

@@ -1,8 +1,8 @@
 /******************************************************************************
  * @file     cachel1_armv7.h
  * @brief    CMSIS Level 1 Cache API for Armv7-M and later
- * @version  V1.0.2
- * @date     22. June 2022
+ * @version  V1.0.3
+ * @date     12. July 2022
  ******************************************************************************/
 /*
  * Copyright (c) 2020-2021 Arm Limited. All rights reserved.
@@ -57,8 +57,10 @@
 __STATIC_FORCEINLINE void SCB_EnableICache (void)
 {
   #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
-    if (SCB->CCR & SCB_CCR_IC_Msk) return;  /* return if ICache is already enabled */
-
+    if (SCB->CCR & SCB_CCR_IC_Msk){ /* return if ICache is already enabled */
+      return; 
+    }
+
     __DSB();
     __ISB();
     SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */
@@ -115,21 +117,23 @@ __STATIC_FORCEINLINE void SCB_InvalidateICache (void)
 __STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (volatile void *addr, int32_t isize)
 {
   #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
-    if ( isize > 0 ) {
-       int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U));
-      uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */;
+    if ( isize <= 0 ) {
+      return;
+    }
 
-      __DSB();
+    int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U));
+    uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */;
 
-      do {
-        SCB->ICIMVAU = op_addr;             /* register accepts only 32byte aligned values, only bits 31..5 are valid */
-        op_addr += __SCB_ICACHE_LINE_SIZE;
-        op_size -= __SCB_ICACHE_LINE_SIZE;
-      } while ( op_size > 0 );
+    __DSB();
 
-      __DSB();
-      __ISB();
-    }
+    do {
+      SCB->ICIMVAU = op_addr;             /* register accepts only 32byte aligned values, only bits 31..5 are valid */
+      op_addr += __SCB_ICACHE_LINE_SIZE;
+      op_size -= __SCB_ICACHE_LINE_SIZE;
+    } while ( op_size > 0 );
+
+    __DSB();
+    __ISB();
   #endif
 }
 
@@ -145,13 +149,14 @@ __STATIC_FORCEINLINE void SCB_EnableDCache (void)
     uint32_t sets;
     uint32_t ways;
 
-    if (SCB->CCR & SCB_CCR_DC_Msk) return;  /* return if DCache is already enabled */
+    if (SCB->CCR & SCB_CCR_DC_Msk){ /* return if DCache is already enabled */
+      return; 
+    }  
 
     SCB->CSSELR = 0U;                       /* select Level 1 data cache */
     __DSB();
 
     ccsidr = SCB->CCSIDR;
-
                                             /* invalidate D-Cache */
     sets = (uint32_t)(CCSIDR_SETS(ccsidr));
     do {
@@ -351,21 +356,23 @@ __STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void)
 __STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int32_t dsize)
 {
   #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
-    if ( dsize > 0 ) {
-       int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
-      uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
+    if ( dsize <= 0 ) {
+      return;
+    }
 
-      __DSB();
+    int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
+    uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
 
-      do {
-        SCB->DCIMVAC = op_addr;             /* register accepts only 32byte aligned values, only bits 31..5 are valid */
-        op_addr += __SCB_DCACHE_LINE_SIZE;
-        op_size -= __SCB_DCACHE_LINE_SIZE;
-      } while ( op_size > 0 );
+    __DSB();
 
-      __DSB();
-      __ISB();
-    }
+    do {
+      SCB->DCIMVAC = op_addr;             /* register accepts only 32byte aligned values, only bits 31..5 are valid */
+      op_addr += __SCB_DCACHE_LINE_SIZE;
+      op_size -= __SCB_DCACHE_LINE_SIZE;
+    } while ( op_size > 0 );
+
+    __DSB();
+    __ISB();
   #endif
 }
 
@@ -381,21 +388,23 @@ __STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int
 __STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (volatile void *addr, int32_t dsize)
 {
   #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
-    if ( dsize > 0 ) {
-       int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
-      uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
+    if ( dsize <= 0 ) {
+       return;
+    }
 
-      __DSB();
+    int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
+    uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
 
-      do {
-        SCB->DCCMVAC = op_addr;             /* register accepts only 32byte aligned values, only bits 31..5 are valid */
-        op_addr += __SCB_DCACHE_LINE_SIZE;
-        op_size -= __SCB_DCACHE_LINE_SIZE;
-      } while ( op_size > 0 );
+    __DSB();
 
-      __DSB();
-      __ISB();
-    }
+    do {
+      SCB->DCCMVAC = op_addr;             /* register accepts only 32byte aligned values, only bits 31..5 are valid */
+      op_addr += __SCB_DCACHE_LINE_SIZE;
+      op_size -= __SCB_DCACHE_LINE_SIZE;
+    } while ( op_size > 0 );
+
+    __DSB();
+    __ISB();
   #endif
 }
 
@@ -411,21 +420,23 @@ __STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (volatile void *addr, int32_t
 __STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (volatile void *addr, int32_t dsize)
 {
   #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
-    if ( dsize > 0 ) {
-       int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
-      uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
+    if ( dsize <= 0 ) {
+       return;
+    }
 
-      __DSB();
+    int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
+    uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
 
-      do {
-        SCB->DCCIMVAC = op_addr;            /* register accepts only 32byte aligned values, only bits 31..5 are valid */
-        op_addr +=          __SCB_DCACHE_LINE_SIZE;
-        op_size -=          __SCB_DCACHE_LINE_SIZE;
-      } while ( op_size > 0 );
+    __DSB();
 
-      __DSB();
-      __ISB();
-    }
+    do {
+      SCB->DCCIMVAC = op_addr;            /* register accepts only 32byte aligned values, only bits 31..5 are valid */
+      op_addr +=          __SCB_DCACHE_LINE_SIZE;
+      op_size -=          __SCB_DCACHE_LINE_SIZE;
+    } while ( op_size > 0 );
+
+    __DSB();
+    __ISB();
   #endif
 }
 

CMSIS/Core/Include/cmsis_armclang.h

@@ -1,8 +1,8 @@
 /**************************************************************************//**
  * @file     cmsis_armclang.h
  * @brief    CMSIS compiler armclang (Arm Compiler 6) header file
- * @version  V5.4.4
- * @date     30. May 2022
+ * @version  V5.4.5
+ * @date     12. July 2022
  ******************************************************************************/
 /*
  * Copyright (c) 2009-2022 Arm Limited. All rights reserved.
@@ -427,7 +427,7 @@ __STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
   uint32_t result;
 
   __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-  return(result);
+  return result;
 }
 
 
@@ -472,7 +472,7 @@ __STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
   uint32_t result;
 
   __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
-  return(result);
+  return result;
 }
 
 
@@ -533,7 +533,7 @@ __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
     {
       return max;
     }
-    else if (val < min)
+    if (val < min)
     {
       return min;
     }
@@ -557,7 +557,7 @@ __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
     {
       return max;
     }
-    else if (val < 0)
+    if (val < 0)
     {
       return 0U;
     }
@@ -616,7 +616,7 @@ __STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
   uint32_t result;
 
   __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
-  return(result);
+  return result;
 }
 
 
@@ -764,7 +764,7 @@ __STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
   uint32_t result;
 
   __ASM volatile ("MRS %0, control" : "=r" (result) );
-  return(result);
+  return result;
 }
 
 
@@ -779,7 +779,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
   uint32_t result;
 
   __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
-  return(result);
+  return result;
 }
 #endif
 
@@ -820,7 +820,7 @@ __STATIC_FORCEINLINE uint32_t __get_IPSR(void)
   uint32_t result;
 
   __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
-  return(result);
+  return result;
 }
 
 
@@ -834,7 +834,7 @@ __STATIC_FORCEINLINE uint32_t __get_APSR(void)
   uint32_t result;
 
   __ASM volatile ("MRS %0, apsr" : "=r" (result) );
-  return(result);
+  return result;
 }
 
 
@@ -848,7 +848,7 @@ __STATIC_FORCEINLINE uint32_t __get_xPSR(void)
   uint32_t result;
 
   __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
-  return(result);
+  return result;
 }
 
 
@@ -862,7 +862,7 @@ __STATIC_FORCEINLINE uint32_t __get_PSP(void)
   uint32_t result;
 
   __ASM volatile ("MRS %0, psp"  : "=r" (result) );
-  return(result);
+  return result;
 }
 
 
@@ -877,7 +877,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
   uint32_t result;
 
   __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
-  return(result);
+  return result;
 }
 #endif
 
@@ -916,7 +916,7 @@ __STATIC_FORCEINLINE uint32_t __get_MSP(void)
   uint32_t result;
 
   __ASM volatile ("MRS %0, msp" : "=r" (result) );
-  return(result);
+  return result;
 }
 
 
@@ -931,7 +931,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
   uint32_t result;
 
   __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
-  return(result);
+  return result;
 }
 #endif
 
@@ -971,7 +971,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
   uint32_t result;
 
   __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
-  return(result);
+  return result;
 }
 
 
@@ -997,7 +997,7 @@ __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
   uint32_t result;
 
   __ASM volatile ("MRS %0, primask" : "=r" (result) );
-  return(result);
+  return result;
 }
 
 
@@ -1012,7 +1012,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
   uint32_t result;
 
   __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
-  return(result);
+  return result;
 }
 #endif
 
@@ -1077,7 +1077,7 @@ __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
   uint32_t result;
 
   __ASM volatile ("MRS %0, basepri" : "=r" (result) );
-  return(result);
+  return result;
 }
 
 
@@ -1092,7 +1092,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
   uint32_t result;
 
   __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
-  return(result);
+  return result;
 }
 #endif
 
@@ -1143,7 +1143,7 @@ __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
   uint32_t result;
 
   __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
-  return(result);
+  return result;
 }
 
 
@@ -1158,7 +1158,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
   uint32_t result;
 
   __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
-  return(result);
+  return result;
 }
 #endif
 
@@ -1493,7 +1493,7 @@ __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
   int32_t result;
 
   __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
-  return(result);
+  return result;
 }
 
 #endif /* (__ARM_FEATURE_DSP == 1) */