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Add UpSample2D Layer Support for Encoder-Decoder Architectures #17

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Add UpSample2D Layer Support for Encoder-Decoder Architectures #17

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@STAmirr STAmirr commented Nov 6, 2025

Summary

Adds support for UpSample2D layers to enable semantic segmentation and encoder-decoder models.

Changes

  • Added XUpSample class in xlayers.py for nearest neighbor upsampling
  • Updated dataflow.py to handle upsampling parameters
  • Uses integer arithmetic (no floating-point operations)
  • Backward compatible with existing models

Aba and others added 30 commits July 8, 2023 17:24
Update testbench structure to allow multiple iterations
439d44d
Fix: multiple iterations
6cddea1
Fix bug in axis_pixels. Update alex_axis_adapter_any for verilator
703746a
Change linux sim to verilator
9657a45
Refactor
eeb2770
Get compiled verilator
e9c8997
Add notebooks for pynq firmware & perfomance
82753e5
Add new bundle from zhenghua
3f635ab
Refactor
b53dbe1
Refactor
43b6459
Add export
ea9350b
Integerate new bundle into param_test
40c324b
Feature: allow CI > WRAM/KH
4a807a4
Entire model in testbench - sv structs
e7f4af2
Replace AXI-Stream output with ping-pong buffer. Works for K!=1
b73b23b
Fix K=1, changed handshake signsls to toggle
a203b4d
Add basic DPI-C firmware for xsim & verilator
38f9b33
Change done_fill to single clock, for interrupt
925a2e2
Moved load_y logic & file writing to runtime.c
c260a4b
Refactor to decouple txt gen; fixed X_BITS error
1a28c12
Migrated to binary file based DMA testbench, with control logic in C.…
928d710 
… Error for BITS!=8
Github actions bitstring
dbd4429
Make verilator happy
5d268c1
Pack N-bit words into 8-bit little endian bytes for DMA
9331920
Fix: tkeep broadcasting for BITS<8
fa2887b
Update vivado scripts to match output BRAM & interrupt
993459c
@abarajithan11
Updated zcu104 script
053fcd4
Update counters in callback with all indices
d0fdae3
Update README
9e3dcec
Write to byte memory from C and read into files
c0c27ff
awengz and others added 27 commits July 22, 2024 14:26
@awengz
synthesis on quartus
ffc8820
@zhenghuama
Verified on FPGA
cc961ce
Added restrict to firmware
6d36dcf
Minor cleanup
c33558c
Tested multiple runs
6523d43
Clean up Bundle_t
dbc19c0
@zhenghuama
Minimize flushing cache
f1fb55f
Make config & mem baseaddr a function argument, to support virtual mem
3e3307c
Add & fix resnet50
3e3bda2
Export performance
25c6d9b
Pointnet works
c7f7889
stuck debug
3645ce1
@awengz
fix stuck.py issue
28004ef
ResNet-50 passed
c1288a8
Add jettagger
e811855
@abarajithan11
Fix example & readme
7b181d4
Minor changes
d90924b
Update package dependancy
94710c5
Add vcd
e76dec5
@abarajithan11
Add optional trace
7a9d8df
Update resnet settings
8703d30
Add matmul
d58e99f
@abarajithan11
Update zcu104
c0c0cf2
@STAmirr
add XUpSample layer for nearest neighbor upsampling functionality to…
a8787b6 
… xlayers
@STAmirr
changed export_inference function to handle optional attributes safel…
be37885 
…y for various layer types like upsample2d, ensuring robustness against weight less layers
@STAmirr
adjusting XBundle class to enhance export functionality for various l…
85c86ed 
…ayer types, including upsample and dense layers.
@STAmirr
enhanced dataflow for upsample2d compatibility
45bd9b5
@abarajithan11 abarajithan11 force-pushed the master branch 2 times, most recently from a9cf54d to ce3f4db Compare December 6, 2025 05:18
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6 participants

@STAmirr @abarajithan11 @zhenghuama @RaviduHM99 @awengz @rck289