spirv-opt: handle mixed-width shifts in RedundantAndShift #6504
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I encountered a crash with instruction foldings enabled while using shaderc (test case 15), this commit adds support for instruction folding for all different cases I interpreted as valid while reading the spirv spec. https://registry.khronos.org/SPIR-V/specs/unified1/SPIRV.html 3.3.14. Bit Instructions
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I encountered a crash with instruction folding enabled while using shaderc (reproduced in test case 15) where shaderc generated code with a 32 shift on a 64bit int, this commit adds support for instruction folding for all different cases I interpreted as valid from reading the spirv spec.
https://registry.khronos.org/SPIR-V/specs/unified1/SPIRV.html 3.3.14. Bit Instructions
To the best of my knowledge this is correct and I added tests
only supports 8/16/32/64 width since that's what I saw defined in the spec but should handle things like https://github.khronos.org/SPIRV-Registry/extensions/ALTERA/SPV_ALTERA_arbitrary_precision_integers.html fine by not folding as it did before while fixing the mixed-width shift case and supporting 8/16