The design of a RISC-V five-stage pipeline at Vivado
The course assignment for Integrated Circuit Design at Southeast University required the design of a RISC-V five-stage pipeline. The project was completed excellently, and 9 out of 10 routines were executed correctly. The last one could not be modified, and needs to be improved in the future. I uploaded it to github to leave a memorial for the four-person team, and to welcome experts to give me suggestions on this broken code project!