perf(riscv64): fast path interrupt polling#1074
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NEMU Performance Results - XS Interpreter
NEMU Performance Results - XS Ref Shared Object
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Skip pending-state assembly when no interrupt is enabled, M-mode has interrupts globally disabled, or NMIE is closed. After a pending bit is observed, compute the effective global-enable mask once. Keeping delegation filtering after get_mip avoids adding get_hideleg to the common no-pending S/U path. Use a static byte-sized priority table so the cold selection path stays compact without rebuilding an array on every query. DynamoRIO shared-ref CoreMark host instructions drop from 6,466,360,574 to 5,507,075,491 (-14.835%) with identical guest instruction counts.
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Pull request overview
Optimizes the RISC-V (riscv64) interrupt polling hot path in isa_query_intr() by adding early-exit checks and reducing work in the common “no interrupt taken” case, while keeping the existing interrupt priority/delegation semantics.
Changes:
- Add fast-path early returns when no interrupts are enabled, M-mode global interrupts are disabled, or NMIE is closed.
- Compute delegation/effective global-enable mask once per poll and apply it to the pending vector before selection.
- Replace per-call priority arrays/loop bounds with a single static byte-sized priority table and iterate via
ARRLEN.
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Optimize the hot RISC-V interrupt polling path in
isa_query_intr().Most polling calls do not result in a taken interrupt. Avoid constructing the pending interrupt state when no interrupt is enabled, M-mode interrupts are globally disabled, or NMIE is closed.
After observing a pending interrupt, compute the effective privilege and delegation mask once. Use a static byte-sized priority table to reduce the overhead of the cold interrupt selection path.
The RISC-V interrupt priority, privilege, delegation, RVH, and Sscofpmf semantics are preserved.
DynamoRIO shared REF CoreMark results with identical guest instruction counts: