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feat(flash): load flash image through image loader#1086

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good-circle merged 1 commit into
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20260614-cpt-pr8
Jul 13, 2026
Merged

feat(flash): load flash image through image loader#1086
good-circle merged 1 commit into
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20260614-cpt-pr8

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@good-circle good-circle commented Jun 20, 2026 •
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Route flash image loading through load_img() instead of open-coding raw fopen/fread handling.

This keeps flash image handling consistent with memory image loading and lets flash reuse the common format detection path.

Base automatically changed from 20260614-cpt-pr7 to master July 6, 2026 05:55
@good-circle
feat(flash): support compressed flash images
583796c 
Flash image loading used to open the file directly with fopen()/fread(), so it only handled raw images and bypassed the common gzip/zstd loaders.

Load flash images through load_img() after the existing flash image lookup succeeds, matching the memory image loading path.
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github-actions Bot commented Jul 12, 2026

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NEMU Performance Results - XS Interpreter

Test Guest Instructions Host Instructions Estimated Host Throughput (instr/s) Actual NEMU Throughput (instr/s) Baseline Host Instructions Baseline Actual NEMU Throughput (instr/s) Change vs Baseline (Instructions)
bitmanip.bin 1.385e+05 5.742e+07 2.412e+07 3.012e+07 5.742e+07 2.681e+07 +0.00%
coremark-riscv64-xs-rv64gc-o2.bin 3.354e+06 1.946e+08 1.723e+08 2.250e+08 1.946e+08 2.187e+08 +0.00%
coremark-riscv64-xs-rv64gc-o3.bin 3.394e+06 1.940e+08 1.750e+08 2.395e+08 1.940e+08 2.264e+08 -0.00%
coremark-riscv64-xs-rv64gcb-o3.bin 3.035e+06 1.911e+08 1.588e+08 2.189e+08 1.911e+08 1.319e+08 +0.00%
amtest-riscv64-xs.bin 1.587e+04 8.829e+06 1.798e+07 2.248e+07 8.829e+06 2.274e+07 -0.00%
aliastest-riscv64-xs.bin 1.376e+03 7.733e+06 1.779e+06 4.794e+06 7.733e+06 3.556e+06 +0.00%
softprefetchtest-riscv64-xs.bin 2.643e+03 7.786e+06 3.395e+06 3.263e+06 7.786e+06 6.494e+06 -0.00%
zacas-riscv64-xs.bin 6.470e+04 1.266e+07 5.110e+07 2.191e+07 1.266e+07 2.043e+07 +0.00%
rvv-workload-suite 4.566e+04 1.111e+08 4.110e+06 4.593e+06 1.111e+08 4.927e+06 -0.00%
linux-hello 6.677e+07 1.688e+10 3.955e+07 5.231e+07 1.688e+10 5.179e+07 -0.00%

NEMU Performance Results - XS Ref Shared Object

Test Guest Instructions Host Instructions Estimated Host Throughput (instr/s) Actual NEMU Throughput (instr/s) Baseline Host Instructions Baseline Actual NEMU Throughput (instr/s) Change vs Baseline (Instructions)
bitmanip.bin 1.385e+05 1.097e+09 1.262e+06 1.290e+06 1.097e+09 1.256e+06 +0.00%
coremark-riscv64-xs-rv64gc-o2.bin 3.354e+06 6.447e+09 5.203e+06 5.384e+06 6.447e+09 5.387e+06 +0.00%
coremark-riscv64-xs-rv64gc-o3.bin 3.394e+06 6.475e+09 5.242e+06 5.411e+06 6.475e+09 5.516e+06 +0.00%
coremark-riscv64-xs-rv64gcb-o3.bin 3.035e+06 6.090e+09 4.983e+06 5.135e+06 6.090e+09 5.138e+06 +0.00%
amtest-riscv64-xs.bin 1.588e+04 3.464e+07 4.583e+06 2.320e+06 3.464e+07 2.546e+06 +0.00%
aliastest-riscv64-xs.bin 1.379e+03 4.878e+06 2.827e+06 6.096e+05 4.878e+06 5.147e+05 +0.00%
softprefetchtest-riscv64-xs.bin 2.646e+03 6.989e+06 3.786e+06 1.091e+06 6.989e+06 1.103e+06 +0.00%
zacas-riscv64-xs.bin 6.471e+04 1.300e+08 4.979e+06 2.365e+06 1.300e+08 3.023e+06 +0.00%
rvv-workload-suite 4.568e+04 4.311e+08 1.060e+06 7.315e+05 4.311e+08 7.127e+05 +0.00%
linux-hello 7.522e+07 6.683e+11 1.125e+06 1.162e+06 6.683e+11 1.168e+06 +0.00%
  • Host Instructions is measured by DynamoRIO's inscount client.
  • Estimated Host Throughput assumes a fixed 4GHz CPU and IPC=2.5.
  • Actual NEMU Throughput is a single native NEMU run and may vary with host CPU performance.
  • Baseline columns are populated on pull_request runs when the PR base contains the same defconfig.
  • Change vs Baseline (Instructions) is computed from host instruction count; positive means fewer host instructions than baseline.

@good-circle good-circle merged commit 464f46f into master Jul 13, 2026
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@good-circle good-circle deleted the 20260614-cpt-pr8 branch July 13, 2026 06:19
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@poemonsense poemonsense poemonsense approved these changes
@Anzooooo Anzooooo Awaiting requested review from Anzooooo Anzooooo is a code owner

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