[dm][clk] refactoring the CLK framework #11029
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The old CLK is can't link all hardware clock cell in system that the API of layout such as 'set_parent' can't work as expected. Some hareware clock cell need some flags to prevent some dangerous behaviors, eg: When a clock cell is link to the PMU, the SoC will power-down if the cell is disable. The new CLK can do it, and make the CLK drivers implemented easier from TRM/DataSheet. Signed-off-by: GuEe-GUI <[email protected]>
Signed-off-by: GuEe-GUI <[email protected]>
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📌 Code Review Assignment🏷️ Tag: componentsReviewers: Maihuanyi Changed Files (Click to expand)
📊 Current Review Status (Last Updated: 2025-12-10 17:25 CST)
📝 Review Instructions
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这个要修复下 |
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不太明白这个报错是什么意思 |
2 participants
拉取/合并请求描述：(PR description)
[
The old CLK is can't link all hardware clock cell in system that the
API of layout such as 'set_parent' can't work as expected.
Some hareware clock cell need some flags to prevent some dangerous behaviors, eg:
When a clock cell is link to the PMU, the SoC will power-down if the cell is
disable.
The new CLK can do it, and make the CLK drivers implemented easier from
TRM/DataSheet.
In the new CLK, the platform device can set default CLK config when probe.
qemu-virt64-aarch64
raspberry-pi/raspi3-64
raspberry-pi/raspi4-64
raspberry-pi/raspi5
rockchip/rk3300
rockchip/rk3500（Not Update now, push the new one in the new PR）
spacemit/k1
]
当前拉取/合并请求的状态 Intent for your PR
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代码质量 Code Quality：
我在这个拉取/合并请求中已经考虑了 As part of this pull request, I've considered the following:
#if 0代码，不包含已经被注释了的代码 All redundant code is removed and cleaned up