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Unify usage of POINTER_SIZE across modules #265

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Merged
cbespin merged 1 commit into from
Apr 17, 2026
Merged

Unify usage of POINTER_SIZE across modules #265

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13 changes: 8 additions & 5 deletions basil/firmware/modules/bram_fifo/bram_fifo_core.v
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Original file line number Diff line number Diff line change
Expand Up @@ -72,6 +72,8 @@ begin
end
end

localparam POINTER_SIZE = 32;

// read reg
wire [31:0] CONF_SIZE_BYTE; // write data count, 1 - 2 - 3, in units of byte
reg [31:0] CONF_SIZE_BYTE_BUF;
Expand Down Expand Up @@ -104,8 +106,10 @@ end

always @(posedge BUS_CLK)
begin
if (BUS_ADD == 4 && BUS_RD)
CONF_SIZE_BYTE_BUF <= CONF_SIZE_BYTE;
if (BUS_ADD == 4 && BUS_RD) begin
// Pad upper bits with 0s if pointer size less than 32
CONF_SIZE_BYTE_BUF <= {{(32-POINTER_SIZE){1'b0}}, CONF_SIZE_BYTE[POINTER_SIZE-1:0]};
end
end

//reg FIFO_READ_NEXT_OUT_BUF;
Expand All @@ -115,11 +119,10 @@ wire FULL_BUF;

assign FIFO_READ_NEXT_OUT = !FULL_BUF;

localparam POINTER_SIZE = 32;

generic_fifo #(
.DATA_SIZE(32),
.DEPTH(DEPTH)
.DEPTH(DEPTH),
.POINTER_SIZE(POINTER_SIZE)
) i_buf_fifo (
.clk(BUS_CLK),
.reset(RST),
Expand Down
5 changes: 2 additions & 3 deletions basil/firmware/modules/utils/generic_fifo.v
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Original file line number Diff line number Diff line change
Expand Up @@ -10,7 +10,8 @@

module generic_fifo #(
parameter DATA_SIZE = 32,
parameter DEPTH = 8
parameter DEPTH = 8,
parameter POINTER_SIZE = 16 // maximum in Xilinx 7-series
)(
clk,
reset,
Expand All @@ -33,8 +34,6 @@ output reg [DATA_SIZE-1:0] data_out;

reg [DATA_SIZE:0] mem [DEPTH-1:0];

localparam POINTER_SIZE = 16;

reg [POINTER_SIZE-1:0] rd_pointer, rd_tmp, wr_pointer;
output reg [POINTER_SIZE-1:0] size;

Expand Down
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