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Fix port width of wrapper in generic_fifo #269

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Merged
rpartzsch merged 1 commit into from
May 8, 2026
Merged

Fix port width of wrapper in generic_fifo #269

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9 changes: 5 additions & 4 deletions basil/firmware/modules/utils/generic_fifo.v
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Original file line number Diff line number Diff line change
Expand Up @@ -105,17 +105,18 @@ endmodule
module gerneric_fifo
#(
parameter DATA_SIZE = 32,
parameter DEPTH = 8
parameter DEPTH = 8,
parameter POINTER_SIZE = 16 // maximum in Xilinx 7-series
) (
input wire clk,
input wire reset,
input wire write,
input wire read,
input wire data_in,
input wire [DATA_SIZE-1:0] data_in,
output wire full,
output wire empty,
output wire data_out,
output wire size
output wire [DATA_SIZE-1:0] data_out,
output wire [POINTER_SIZE-1:0] size
);

generic_fifo #(
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