BOOLEAN_FUNCTION_MINIMIZATION

AIM:

To implement the given logic function verify its operation in Quartus using Verilog programming.

F1= A’B’C’D’+AC’D’+B’CD’+A’BCD+BC’D

F2=xy’z+x’y’z+w’xy+wx’y+wxy

Equipment Required:

Hardware – PCs, Cyclone II , USB flasher

Software – Quartus prime

Procedure

1. Type the program in Quartus software.

2. Compile and run the program.

3. Generate the RTL schematic and save the logic diagram.

4. Create nodes for inputs and outputs to generate the timing diagram.

5. For different input combinations generate the timing diagram.

BOOLEAN MINIMIZATION

TRUTH TABLE:

i)F1

ii)F2

Program:

Program to implement the given logic function and to verify its operations in quartus using Verilog programming.

module form(a,b,c,d,f1);
input a,b,c,d;
output f1;
assign f1=((~b&~d)|(~a&b&d)|(a&b&~c));
endmodule

module Form2(x,y,z,w,f2);
input x,y,z,w;
output f2;
assign f2=((~y&z)|(x&y)|(w&y));
endmodule

Developed by:Thilak raj .P

RegisterNumber:24900585

RTL

F1 F2

Output:

F1 F2

Result:

Thus the given logic functions are implemented using and their operations are verified using Verilog programming.