It is intended to build a 32-bit:
- pipeline RISC-V processor;
Firstly, clone the repo:
$ git clone git@github.com:TomasLAbreu/riscv-processor.git
$ cd riscv-processor/
- RISC-V Instruction Set Specifications
- RISC-V Instruction Set Manual
- RISC-V Instruction Set Summary
- RISC-V Reference Card
- Digital Design and Computer Architecture RISC-V Edition - Chapter 7 (PDF pages 421-470)
The RISC-V core supports the following ISA instructions:
I Type
- lb
- lh
- lw
- lbu
- lhu
- addi
- slli
- slti
- sltiu
- xori
- srli
- srai
- ori
- andi
- jalr
S Type
- sb
- sh
- sw
R Type
- add
- sub
- sll
- slt
- sltu
- xor
- srl
- sra
- or
- and
U Type
- auipc
- lui
B Type
- beq
- bne
- blt
- bge
- bltu
- bgeu
J Type
- jal