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Fix Interrupt Handling and Critical Section for V3A based chips (CH32V103, CH565, CH569, CH571, CH573)#21

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aq1018 wants to merge 3 commits intoch32-rs:mainfrom
OpenServoCore:fix/v3a-interrupt
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Fix Interrupt Handling and Critical Section for V3A based chips (CH32V103, CH565, CH569, CH571, CH573)#21
aq1018 wants to merge 3 commits intoch32-rs:mainfrom
OpenServoCore:fix/v3a-interrupt

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@aq1018 aq1018 commented Apr 15, 2026

Problem

When I was working with CH32V103, any Interrupt or Critical Section usage cause the chip to hang. I was able to trace the problem to how V3A is different than other V3 chips in two ways:

  1. V3A has no VectoredAddress support for interrupt handling.
  2. V3A has "invalid" gintenr register. ( Documented in the reference manual )

Fix

Interrupt Handling

In this PR, I opted to use Direct trap mode, because VectoredJump trap mode would require generating a jump instruction based vector table instead of the current address based vector table.

Anyways, the solution in the PR hooks the mtvec address to a _unified_trap_handler. This handler then reads mcause, looks up handler address from the address based vector table, and jumps to it. Both highcode and non-highcode cases are covered.

Critical Section

The reference manual says gintenr is invalid for V3A, so this PR uses mstatus instead, the same way as V2.

@aq1018 aq1018 force-pushed the fix/v3a-interrupt branch from fc52be7 to 4adfda8 Compare April 15, 2026 07:40
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