UVM Synchronous FIFO Verification Project

Overview

This repository contains a Synchronous FIFO design and a complete UVM (Universal Verification Methodology) testbench. VsCode and Questasim have been used.

Key Features

• Parameterizable Design: Adjustable data width and FIFO depth.
• UVM Testbench: Includes a full UVM hierarchy (Sequencer, Driver, Monitor, Scoreboard).
• Advanced Monitoring: Implemented a non-blocking monitor to handle RTL-to-testbench timing latency.
• Functional Coverage: Coverage bins to track empty, full, and simultaneous read/write scenarios.
• Automation: TCL scripts included for automated simulation in QuestaSim.

How to Run

1. Clone the repository.
2. Open QuestaSim.
3. Run do sim/run.tcl (or your specific script name).