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Merge pull request #864 from diffblue/verilog-named-sequence
SystemVerilog: named sequences
2 parents 798b5e0 + 25636cf commit 5f864c0

11 files changed

+165
-1
lines changed

‎CHANGELOG

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@@ -6,6 +6,7 @@
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* BMC: support SVA sequence intersect
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* SystemVerilog: streaming concatenation {<<{...}} and {>>{...}}
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* SystemVerilog: set membership operator
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* SystemVerilog: named sequences
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# EBMC 5.3
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‎regression/verilog/SVA/named_sequence1.desc

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@@ -0,0 +1,9 @@
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CORE
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named_sequence1.sv
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--bound 0
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^\[main\.assert\.1\] always main\.x_is_ten: PROVED up to bound 0$
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^EXIT=0$
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^SIGNAL=0$
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--
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^warning: ignoring
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--

‎regression/verilog/SVA/named_sequence1.sv

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@@ -0,0 +1,16 @@
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module main(input clk);
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wire [31:0] x = 10;
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sequence x_is_ten;
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x == 10 ##1 x >= 0
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endsequence : x_is_ten
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assert property (x_is_ten);
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sequence x_is_twenty;
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// the ; is optional
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x == 20;
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endsequence : x_is_twenty
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endmodule

‎src/hw_cbmc_irep_ids.h

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@@ -96,6 +96,7 @@ IREP_ID_ONE(verilog_indexed_part_select_plus)
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IREP_ID_ONE(verilog_indexed_part_select_minus)
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IREP_ID_ONE(verilog_past)
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IREP_ID_ONE(verilog_property_declaration)
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IREP_ID_ONE(verilog_sequence_declaration)
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IREP_ID_ONE(verilog_value_range)
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IREP_ID_ONE(verilog_void)
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IREP_ID_ONE(verilog_streaming_concatenation_left_to_right)

‎src/verilog/parser.y

Lines changed: 45 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2245,11 +2245,12 @@ expect_property_statement: TOK_EXPECT '(' property_spec ')' action_block
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assertion_item_declaration:
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property_declaration
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| sequence_declaration
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;
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property_declaration:
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TOK_PROPERTY property_identifier property_port_list_paren_opt ';'
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property_spec
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property_spec semicolon_opt
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TOK_ENDPROPERTY property_identifier_opt
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{ init($$, ID_verilog_property_declaration);
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stack_expr($$).set(ID_base_name, stack_expr($2).id());
@@ -2386,6 +2387,47 @@ property_case_item:
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{ init($$, ID_case_item); mto($$, $3); }
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;
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sequence_declaration:
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"sequence" { init($$, ID_verilog_sequence_declaration); }
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sequence_identifier sequence_port_list_opt ';'
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sequence_expr semicolon_opt
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"endsequence" sequence_identifier_opt
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{ $$=$2;
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stack_expr($$).set(ID_base_name, stack_expr($3).id());
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mto($$, $6);
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}
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;
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sequence_port_list_opt:
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/* Optional */
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{ init($$); }
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| '(' ')'
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{ init($$); }
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| '(' sequence_port_list ')'
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{ $$=$2; }
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;
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sequence_port_list:
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sequence_port_item
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{ init($$); mto($$, $1); }
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| sequence_port_list sequence_port_item
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{ $$=$1; mto($$, $2); }
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;
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sequence_port_item:
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formal_port_identifier
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;
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sequence_identifier_opt:
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/* Optional */
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| TOK_COLON sequence_identifier
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;
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semicolon_opt:
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/* Optional */
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| ';'
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;
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expression_or_dist_brace:
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expression_or_dist
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{ init($$, "patterns"); mto($$, $1); }
@@ -4202,6 +4244,8 @@ identifier: non_type_identifier;
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property_identifier: TOK_NON_TYPE_IDENTIFIER;
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sequence_identifier: TOK_NON_TYPE_IDENTIFIER;
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variable_identifier: identifier;
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%%

‎src/verilog/verilog_elaborate.cpp

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@@ -118,6 +118,11 @@ void verilog_typecheckt::collect_symbols(
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{
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}
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void verilog_typecheckt::collect_symbols(
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const verilog_sequence_declarationt &declaration)
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{
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}
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void verilog_typecheckt::collect_symbols(const typet &type)
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{
123128
// These types are not yet converted.
@@ -843,6 +848,10 @@ void verilog_typecheckt::collect_symbols(
843848
{
844849
collect_symbols(to_verilog_property_declaration(module_item));
845850
}
851+
else if(module_item.id() == ID_verilog_sequence_declaration)
852+
{
853+
collect_symbols(to_verilog_sequence_declaration(module_item));
854+
}
846855
else
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DATA_INVARIANT(false, "unexpected module item: " + module_item.id_string());
848857
}

‎src/verilog/verilog_expr.h

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@@ -2782,6 +2782,44 @@ to_verilog_property_declaration(exprt &expr)
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return static_cast<verilog_property_declarationt &>(expr);
27832783
}
27842784

2785+
class verilog_sequence_declarationt : public verilog_module_itemt
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{
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public:
2788+
explicit verilog_sequence_declarationt(exprt sequence)
2789+
{
2790+
add_to_operands(std::move(sequence));
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}
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const irep_idt &base_name() const
2794+
{
2795+
return get(ID_base_name);
2796+
}
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2798+
const exprt &sequence() const
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{
2800+
return op0();
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}
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exprt &sequence()
2804+
{
2805+
return op0();
2806+
}
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};
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inline const verilog_sequence_declarationt &
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to_verilog_sequence_declaration(const exprt &expr)
2811+
{
2812+
PRECONDITION(expr.id() == ID_verilog_sequence_declaration);
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return static_cast<const verilog_sequence_declarationt &>(expr);
2814+
}
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2816+
inline verilog_sequence_declarationt &
2817+
to_verilog_sequence_declaration(exprt &expr)
2818+
{
2819+
PRECONDITION(expr.id() == ID_verilog_sequence_declaration);
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return static_cast<verilog_sequence_declarationt &>(expr);
2821+
}
2822+
27852823
class verilog_streaming_concatenation_exprt : public exprt
27862824
{
27872825
public:

‎src/verilog/verilog_interfaces.cpp

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@@ -306,6 +306,9 @@ void verilog_typecheckt::interface_module_item(
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else if(module_item.id() == ID_verilog_property_declaration)
307307
{
308308
}
309+
else if(module_item.id() == ID_verilog_sequence_declaration)
310+
{
311+
}
309312
else
310313
{
311314
DATA_INVARIANT(false, "unexpected module item: " + module_item.id_string());

‎src/verilog/verilog_synthesis.cpp

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@@ -3305,6 +3305,9 @@ void verilog_synthesist::synth_module_item(
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else if(module_item.id() == ID_verilog_property_declaration)
33063306
{
33073307
}
3308+
else if(module_item.id() == ID_verilog_sequence_declaration)
3309+
{
3310+
}
33083311
else
33093312
{
33103313
throw errort().with_location(module_item.source_location())

‎src/verilog/verilog_typecheck.cpp

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@@ -1737,6 +1737,10 @@ void verilog_typecheckt::convert_module_item(
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{
17381738
convert_property_declaration(to_verilog_property_declaration(module_item));
17391739
}
1740+
else if(module_item.id() == ID_verilog_sequence_declaration)
1741+
{
1742+
convert_sequence_declaration(to_verilog_sequence_declaration(module_item));
1743+
}
17401744
else
17411745
{
17421746
throw errort().with_location(module_item.source_location())
@@ -1781,6 +1785,40 @@ void verilog_typecheckt::convert_property_declaration(
17811785

17821786
/*******************************************************************\
17831787
1788+
Function: verilog_typecheckt::convert_sequence_declaration
1789+
1790+
Inputs:
1791+
1792+
Outputs:
1793+
1794+
Purpose:
1795+
1796+
\*******************************************************************/
1797+
1798+
void verilog_typecheckt::convert_sequence_declaration(
1799+
verilog_sequence_declarationt &declaration)
1800+
{
1801+
auto base_name = declaration.base_name();
1802+
auto full_identifier = hierarchical_identifier(base_name);
1803+
1804+
convert_sva(declaration.sequence());
1805+
1806+
auto type = bool_typet{};
1807+
type.set(ID_C_verilog_type, ID_verilog_sequence_declaration);
1808+
symbolt symbol{full_identifier, type, mode};
1809+
1810+
symbol.module = module_identifier;
1811+
symbol.base_name = base_name;
1812+
symbol.pretty_name = strip_verilog_prefix(symbol.name);
1813+
symbol.is_macro = true;
1814+
symbol.value = declaration.sequence();
1815+
symbol.location = declaration.source_location();
1816+
1817+
add_symbol(std::move(symbol));
1818+
}
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1820+
/*******************************************************************\
1821+
17841822
Function: verilog_typecheckt::convert_statements
17851823
17861824
Inputs:

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