Verilog: add missing expression precedences #1390

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Open

kroening wants to merge 1 commit into main from verilog-precedences

Collaborator

kroening commented Nov 6, 2025

This adds the missing precedences for some Verilog operators.


          Verilog: add missing expression precedences

e73ac32

This adds the missing precedences for some Verilog operators.

kroening added the Verilog label

kroening marked this pull request as ready for review

November 6, 2025 21:22

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels