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[GlobalISel] Preserve destination type kind when lowering G_EXTRACT (llvm#218345)
Use the destination LLT kind when selecting the scalar type used to lower G_EXTRACT. Any-scalar destinations continue using sN, while specific integer or pointer destinations use iN. Gap uncovered when adding CSE support for GISel Post-Legalizer combiner. llvm#217258 Assisted-by: Codex --------- Signed-off-by: Keshav Vinayak Jha <keshavvinayakjha@gmail.com>
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5 files changed

Lines changed: 40 additions & 40 deletions

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‎llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -9913,7 +9913,7 @@ LegalizerHelper::lowerExtract(MachineInstr &MI) {
99139913
(SrcTy.isVector() && DstTy == SrcTy.getElementType()))) {
99149914
LLT SrcIntTy = SrcTy;
99159915
if (!SrcTy.isScalar()) {
9916-
SrcIntTy = LLT::scalar(SrcTy.getSizeInBits());
9916+
SrcIntTy = LLT::integer(SrcTy.getSizeInBits());
99179917
SrcReg = MIRBuilder.buildCast(SrcIntTy, SrcReg).getReg(0);
99189918
}
99199919

‎llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-extract.mir‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -320,13 +320,13 @@ body: |
320320
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
321321
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
322322
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C1]](s64)
323-
; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[BUILD_VECTOR]](<2 x s64>)
324-
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[BITCAST]](s128)
325-
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
326-
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C2]](s32)
327-
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C2]](s32)
328-
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]]
329-
; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[OR]](s64)
323+
; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(i128) = G_BITCAST [[BUILD_VECTOR]](<2 x s64>)
324+
; CHECK-NEXT: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[BITCAST]](i128)
325+
; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 32
326+
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(i64) = G_LSHR [[UV]], [[C2]](i32)
327+
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i64) = G_SHL [[UV1]], [[C2]](i32)
328+
; CHECK-NEXT: [[OR:%[0-9]+]]:_(i64) = G_OR [[LSHR]], [[SHL]]
329+
; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[OR]](i64)
330330
%0:_(s64) = G_CONSTANT i64 0
331331
%1:_(s64) = G_CONSTANT i64 1
332332
%2:_(<2 x s64>) = G_BUILD_VECTOR %0, %1

‎llvm/test/CodeGen/AMDGPU/GlobalISel/global-value.ll‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -142,8 +142,8 @@ define ptr addrspace(6) @external_constant32_got() {
142142
; GCN: bb.1 (%ir-block.0):
143143
; GCN-NEXT: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p4) = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @external_constant32, target-flags(amdgpu-gotprel32-hi) @external_constant32, implicit-def $scc
144144
; GCN-NEXT: [[LOAD:%[0-9]+]]:_(p4) = G_LOAD [[SI_PC_ADD_REL_OFFSET]](p4) :: (dereferenceable invariant load (p4) from got, addrspace 4)
145-
; GCN-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[LOAD]](p4)
146-
; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[PTRTOINT]](s64)
145+
; GCN-NEXT: [[PTRTOINT:%[0-9]+]]:_(i64) = G_PTRTOINT [[LOAD]](p4)
146+
; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[PTRTOINT]](i64)
147147
; GCN-NEXT: [[INTTOPTR:%[0-9]+]]:_(p6) = G_INTTOPTR [[TRUNC]](i32)
148148
; GCN-NEXT: $vgpr0 = COPY [[INTTOPTR]](p6)
149149
; GCN-NEXT: SI_RETURN implicit $vgpr0
@@ -161,8 +161,8 @@ define ptr addrspace(6) @internal_constant32_pcrel() {
161161
; GCN-LABEL: name: internal_constant32_pcrel
162162
; GCN: bb.1 (%ir-block.0):
163163
; GCN-NEXT: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p4) = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @internal_constant32, target-flags(amdgpu-rel32-hi) @internal_constant32, implicit-def $scc
164-
; GCN-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[SI_PC_ADD_REL_OFFSET]](p4)
165-
; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[PTRTOINT]](s64)
164+
; GCN-NEXT: [[PTRTOINT:%[0-9]+]]:_(i64) = G_PTRTOINT [[SI_PC_ADD_REL_OFFSET]](p4)
165+
; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[PTRTOINT]](i64)
166166
; GCN-NEXT: [[INTTOPTR:%[0-9]+]]:_(p6) = G_INTTOPTR [[TRUNC]](i32)
167167
; GCN-NEXT: $vgpr0 = COPY [[INTTOPTR]](p6)
168168
; GCN-NEXT: SI_RETURN implicit $vgpr0

‎llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -186,8 +186,8 @@ body: |
186186
; GCN-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
187187
; GCN-NEXT: [[C:%[0-9]+]]:_(p5) = G_CONSTANT i32 -1
188188
; GCN-NEXT: [[C1:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
189-
; GCN-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY]](p0)
190-
; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[PTRTOINT]](s64)
189+
; GCN-NEXT: [[PTRTOINT:%[0-9]+]]:_(i64) = G_PTRTOINT [[COPY]](p0)
190+
; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[PTRTOINT]](i64)
191191
; GCN-NEXT: [[INTTOPTR:%[0-9]+]]:_(p5) = G_INTTOPTR [[TRUNC]](i32)
192192
; GCN-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](p0), [[C1]]
193193
; GCN-NEXT: [[SELECT:%[0-9]+]]:_(p5) = G_SELECT [[ICMP]](s1), [[INTTOPTR]], [[C]]
@@ -257,8 +257,8 @@ body: |
257257
; GCN-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
258258
; GCN-NEXT: [[C:%[0-9]+]]:_(p3) = G_CONSTANT i32 -1
259259
; GCN-NEXT: [[C1:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
260-
; GCN-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY]](p0)
261-
; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[PTRTOINT]](s64)
260+
; GCN-NEXT: [[PTRTOINT:%[0-9]+]]:_(i64) = G_PTRTOINT [[COPY]](p0)
261+
; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[PTRTOINT]](i64)
262262
; GCN-NEXT: [[INTTOPTR:%[0-9]+]]:_(p3) = G_INTTOPTR [[TRUNC]](i32)
263263
; GCN-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](p0), [[C1]]
264264
; GCN-NEXT: [[SELECT:%[0-9]+]]:_(p3) = G_SELECT [[ICMP]](s1), [[INTTOPTR]], [[C]]
@@ -330,13 +330,13 @@ body: |
330330
; GCN-NEXT: [[UV:%[0-9]+]]:_(p0), [[UV1:%[0-9]+]]:_(p0) = G_UNMERGE_VALUES [[COPY]](<2 x p0>)
331331
; GCN-NEXT: [[C:%[0-9]+]]:_(p3) = G_CONSTANT i32 -1
332332
; GCN-NEXT: [[C1:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
333-
; GCN-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[UV]](p0)
334-
; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[PTRTOINT]](s64)
333+
; GCN-NEXT: [[PTRTOINT:%[0-9]+]]:_(i64) = G_PTRTOINT [[UV]](p0)
334+
; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[PTRTOINT]](i64)
335335
; GCN-NEXT: [[INTTOPTR:%[0-9]+]]:_(p3) = G_INTTOPTR [[TRUNC]](i32)
336336
; GCN-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV]](p0), [[C1]]
337337
; GCN-NEXT: [[SELECT:%[0-9]+]]:_(p3) = G_SELECT [[ICMP]](s1), [[INTTOPTR]], [[C]]
338-
; GCN-NEXT: [[PTRTOINT1:%[0-9]+]]:_(s64) = G_PTRTOINT [[UV1]](p0)
339-
; GCN-NEXT: [[TRUNC1:%[0-9]+]]:_(i32) = G_TRUNC [[PTRTOINT1]](s64)
338+
; GCN-NEXT: [[PTRTOINT1:%[0-9]+]]:_(i64) = G_PTRTOINT [[UV1]](p0)
339+
; GCN-NEXT: [[TRUNC1:%[0-9]+]]:_(i32) = G_TRUNC [[PTRTOINT1]](i64)
340340
; GCN-NEXT: [[INTTOPTR1:%[0-9]+]]:_(p3) = G_INTTOPTR [[TRUNC1]](i32)
341341
; GCN-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](p0), [[C1]]
342342
; GCN-NEXT: [[SELECT1:%[0-9]+]]:_(p3) = G_SELECT [[ICMP1]](s1), [[INTTOPTR1]], [[C]]
@@ -418,8 +418,8 @@ body: |
418418
; GCN: liveins: $vgpr0_vgpr1
419419
; GCN-NEXT: {{ $}}
420420
; GCN-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
421-
; GCN-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY]](p4)
422-
; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[PTRTOINT]](s64)
421+
; GCN-NEXT: [[PTRTOINT:%[0-9]+]]:_(i64) = G_PTRTOINT [[COPY]](p4)
422+
; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[PTRTOINT]](i64)
423423
; GCN-NEXT: [[INTTOPTR:%[0-9]+]]:_(p6) = G_INTTOPTR [[TRUNC]](i32)
424424
; GCN-NEXT: $vgpr0 = COPY [[INTTOPTR]](p6)
425425
%0:_(p4) = COPY $vgpr0_vgpr1
@@ -477,8 +477,8 @@ body: |
477477
; GCN: liveins: $vgpr0_vgpr1
478478
; GCN-NEXT: {{ $}}
479479
; GCN-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
480-
; GCN-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY]](p0)
481-
; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[PTRTOINT]](s64)
480+
; GCN-NEXT: [[PTRTOINT:%[0-9]+]]:_(i64) = G_PTRTOINT [[COPY]](p0)
481+
; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[PTRTOINT]](i64)
482482
; GCN-NEXT: [[INTTOPTR:%[0-9]+]]:_(p6) = G_INTTOPTR [[TRUNC]](i32)
483483
; GCN-NEXT: $vgpr0 = COPY [[INTTOPTR]](p6)
484484
%0:_(p0) = COPY $vgpr0_vgpr1

‎llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir‎

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -1006,10 +1006,10 @@ body: |
10061006
; CHECK: liveins: $vgpr0
10071007
; CHECK-NEXT: {{ $}}
10081008
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
1009-
; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
1010-
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
1011-
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
1012-
; CHECK-NEXT: $vgpr0 = COPY [[LSHR]](s32)
1009+
; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x s16>)
1010+
; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
1011+
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
1012+
; CHECK-NEXT: $vgpr0 = COPY [[LSHR]](i32)
10131013
%0:_(<2 x s16>) = COPY $vgpr0
10141014
%1:_(s16) = G_EXTRACT %0, 1
10151015
%2:_(s32) = G_ANYEXT %1
@@ -1026,10 +1026,10 @@ body: |
10261026
; CHECK: liveins: $vgpr0
10271027
; CHECK-NEXT: {{ $}}
10281028
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
1029-
; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
1030-
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
1031-
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
1032-
; CHECK-NEXT: $vgpr0 = COPY [[LSHR]](s32)
1029+
; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x s16>)
1030+
; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 8
1031+
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
1032+
; CHECK-NEXT: $vgpr0 = COPY [[LSHR]](i32)
10331033
%0:_(<2 x s16>) = COPY $vgpr0
10341034
%1:_(s16) = G_EXTRACT %0, 8
10351035
%2:_(s32) = G_ANYEXT %1
@@ -1140,8 +1140,8 @@ body: |
11401140
; CHECK: liveins: $vgpr0
11411141
; CHECK-NEXT: {{ $}}
11421142
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
1143-
; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY]](p3)
1144-
; CHECK-NEXT: $vgpr0 = COPY [[PTRTOINT]](s32)
1143+
; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(i32) = G_PTRTOINT [[COPY]](p3)
1144+
; CHECK-NEXT: $vgpr0 = COPY [[PTRTOINT]](i32)
11451145
%0:_(p3) = COPY $vgpr0
11461146
%1:_(s16) = G_EXTRACT %0, 0
11471147
%2:_(s32) = G_ANYEXT %1
@@ -1158,10 +1158,10 @@ body: |
11581158
; CHECK: liveins: $vgpr0
11591159
; CHECK-NEXT: {{ $}}
11601160
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
1161-
; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY]](p3)
1162-
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
1163-
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[PTRTOINT]], [[C]](s32)
1164-
; CHECK-NEXT: $vgpr0 = COPY [[LSHR]](s32)
1161+
; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(i32) = G_PTRTOINT [[COPY]](p3)
1162+
; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
1163+
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[PTRTOINT]], [[C]](i32)
1164+
; CHECK-NEXT: $vgpr0 = COPY [[LSHR]](i32)
11651165
%0:_(p3) = COPY $vgpr0
11661166
%1:_(s16) = G_EXTRACT %0, 1
11671167
%2:_(s32) = G_ANYEXT %1
@@ -1428,8 +1428,8 @@ body: |
14281428
; CHECK: liveins: $vgpr0_vgpr1
14291429
; CHECK-NEXT: {{ $}}
14301430
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
1431-
; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY]](p0)
1432-
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[PTRTOINT]](s64)
1431+
; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(i64) = G_PTRTOINT [[COPY]](p0)
1432+
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[PTRTOINT]](i64)
14331433
; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p3) = G_INTTOPTR [[TRUNC]](i32)
14341434
; CHECK-NEXT: $vgpr0 = COPY [[INTTOPTR]](p3)
14351435
%0:_(p0) = COPY $vgpr0_vgpr1

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