esp-20.1.1_20250829

Changes since esp-19.1.2_20250312:

Features:

• Rebased on upstream LLVM 20.1.1
• [Xtensa][MC] Added support for _bnez.n and _beqz.n alias instructions.
• [ESP32-P4][Pass] Added optimization pass which lowers memcpy to the optimized sequence of ESP32-P4 SIMD instructions.

Fixes:

• [Xtensa] Fixed VASTART lowering. Regression in upstream Xtensa backend led to the incorrect variadic arguments passing on stack. The problem was caught in IDF application when code generated by GCC calls variable args function compiled by clang.
• [ESP32P4] Fixed vldbc.8.ip/vldbc.16.ip instructions immediate range. Correct step for immediate value in vldbc.8.ip is 1 and 2 for vldbc.16.ip.
• [Xtensa] Fixed duplicated CPI symbols with text section literals. Close #113.
• [Toolchain][Espressif] Synced runtime libs logic with baremetal toolchain class.

esp-19.1.2_20250312

Changes since esp-19.1.2_20250225:

Fixes:

• [Espressif] Replaced esp-helper script with esp-clang-libs.info to keep version in standalone libs distro

esp-19.1.2_20250225

Changes since esp-19.1.2_20250211:

Fixes:

• [Clang] Fixed missed release tag in --version output

esp-19.1.2_20250211

Changes since esp-18.1.2_20240912:

Features:

• Upgraded to LLVM 19.1.2.
• [Clangd] Return Includes for documentSymbol request. This solves part of the problem related to missed includes in Outline view. Described here.
• [Xtensa] Added fp16 conversion support. It fixes #103 and #91.
• [Xtensa] Added +forced-atomics target feature support. Solves #105.
• [Toolchain] [Espressif] Upgraded libgcc and libstdc++ from GCC 14.2.0.
• [Toolchain] [Espressif] Upgraded GNU binutils version to 2.43.1.
• [Toolchain] [Espressif] [RISCV] Added Zcmt and Zcmp support to GNU binutils.
• [Toolchain] [Espressif] [RISCV] Added multilibs for Z-extensions (zba, zbb, zbc, zbs).
• [Toolchain] [Espressif] Added helper script to support versioning of standalone libraries distribution. Toolchain's distribution part of the solution for #108.
• [Toolchain] [Espressif] [ESP32P4] Added SplitLoopByLength, CustomLICM and LoopUnrollAndRemainder optimization passes to generate faster code for DSP function implementations like FIR, SQRT etc.

Fixes:
[Xtensa] Fixed issue appeared when allocating objects on stack with alignment more then 32 bytes. That could lead to unaligned address of objects accessed via pointer API.

• [Xtensa] Implement XtensaNullTargetStreamer. It fixes crash in Xtensa AsmParser::run() during ModuleSummaryIndexAnalysis pass.
• [Xtensa] Default to unsigned char. Align with GCC behaviour.
• [Xtensa] [ESP32S3] Fixed TIE format_32 encoding and disassembler ambiguities between x24 and format_32 encoding. llvm-objdump had a problem of determining whether it is x24 or format_32 instruction. format_32 encoding was wrong and now fixed to match the TRM.
• [Xtensa] [ESP32S3] Fixed verifier issues in instructions with INOUT operands. Without constraints -verify-machineinstrs failed. Also, without constraints llvm-objdump treated inout registers as 2 different operands which led objdump to think that an instruction had one extra argument.
• [Toolchain] [Espressif] [Newlib]: fix tgammaf(-inf) return value (espressif/esp-idf#14273)
• [Toolchain] [Espressif]: Mingw standalone libs distro contained binutils which should not be part of it.

esp-18.1.2_20240912

Changes since esp-18.1.2_20240829:

Fixes:

• [Xtensa] Fix atomic store operands order. In LLVM 18 atomic store operands order was changed https://reviews.llvm.org/D123143.

esp-18.1.2_20240829

Changes since esp-18.1.2_20240815:

Fixes:

• [RISCV] Fixed registers class for esp32p4 HW loop instructions. Removed unnecessary registers operands limits for HW loop instructions.
• [Toolchain][Espressif] Added 'xesppie' multilib variant mapping for esp32p4. Fixed warning: no multilib found matching flags when xesppie extension is enabled.
• [RISCV][ESP32P4] Don't yet consider v16i8 and v4i32 legal. W/o this fix Clang crashed when tried to select instruction for v16i8 and v4i32 types.

esp-18.1.2_20240815

Changes since esp-17.0.1_20240419:

Features:

• Upgraded LLVM ver to 18.1.2.
• [RISCV] Support for ESP32-P4 custom instructions in RISCV backend.
• [RISCV] Add support for user trap CSRs.
• [Xtensa] Added support for asm underscore prefix which prevents assembler from replacing instructions with their equivalents (single or multiple instructions) when it is applicable.

esp-17.0.1_20240419

Changes (since esp-17.0.1_20240408):

Fixes:

• [Xtensa] Fix issue with adding scavenging frame index. Fixes bug introduced in 50f918b which led to missed spill slot and error like LLVM ERROR: Error while trying to spill A9 from class AR: Cannot scavenge register without an emergency spill slot!.
• [Toolchain][Espressif] Include clangd into distribution. Close #93

esp-17.0.1_20240408

Changes (since esp-16.0.4-20231113):

Features:

• Upgraded LLVM ver to 17.0.1.
• [Toolchain][Espressif]: Upgraded binutils version to 'esp-2.41.0_20240305'.
• [Toolchain][Espressif]: Upgraded newlib version to 'esp-4.3.0_20240322'.
• [Toolchain][Espressif]: Upgraded libstdc++ and libgcc to '13.2.0_20240305'.
• [Toolchain][RISCV][Xtensa] Added Espressif baremetal toolchain.
• [Toolchain][RISCV][Xtensa] Removed GCC installation support for Espressif toolchain. Now picking up multilibs from existing GCC installation is not possible.
• [RISCV] Add 'tcontrol' CSR register.
• [Xtensa] Add predefined macros for core configuration. Now every configrable option for Xtensa core can be checked using pre-defined macro as it is done in GCC 13.
• [Xtensa] Implement support for __attribute__((short__call)) and __attribute__((near)). Related to #90.
• [Xtensa] Add vector conversion builtins. Closes #89.
• [Xtensa] Add support for boolean vectors. Closes #89.
• [Xtensa] Add HIFI3 C types and intrinsics. Closes #89.
• [Xtensa] Add HIFI3 target feature. Closes #89.
• [Xtensa] Make assembler output compatible with GAS. Some Xtensa targets may still use GAS as a default assembler through '-fno-integrated-as option'. These changes make the assembly output compatible with GAS by default.
• [Xtensa] Add Cannonlake CPU. Added a definition of Xtensa LX6 CPU variant present in Intel Cannonlake and Tigerlake SOC platforms. Closes #89.
• [Xtensa] Add float intrinsics. Closes #89.
• [Xtensa] Implement conditional move instrinsics. Closes #89.
• [Xtensa] Add Boolean Extension feature. Closes #89.
• [Xtensa] Add definition of S3 output registers. Xtensa S3 DSP instructions are coded using explicit register allocation. However, some instructions miss RegState:Define flag for output registers. This leads MachineVerifier to raise errors.

Bug Fixes:

• [Toolchain][Espressif] Use custom prefixes for 'as' and 'ld'. To avoid conflicts with 'as' and 'ld' installed as part of IDF GCC-based toolchains. These tools will be replaced with integrated assembler and LLD in future.
• [LLVM][Xtensa] Remove DFP accelrator feature from ESP32-S3.
• [Xtensa] Fix disassembler. Fix disassembling of the Imm8_sh8, Imm64n_4n, Offset8m32, Entry_Imm12 immedaite operands.
• [Clang] Fix undefined std::errc::state_not_recoverable for MinGW build. Replaced with std::errc::not_supported error code.

esp-16.0.4-20231113

Changes (since esp-16.0.0-20230516):

Features:

• Rebased on LLVM 16.0.4
• [Xtensa] Implement CTLZ/CTTZ with NSAU. Closes #77.
• [Xtensa] Handle musttail. Closes #73.
• [Xtensa] Add MINMAX and CLAMPS feature. Closes #78.
• [Xtensa] Add support for ESP32 S3 DSP instructions. The instructions are supported via clang builtins only, which are basically 1-1 mapping to asm instructions.
• [Xtensa] Connect abs to llvm.abs. Closes #78.
• [Xtensa] Configurable FAST int types size. Implemented special option -mfast-int-min32 to workaround compatibility problem with Xtensa GCC's backend which defines size of FAST int types as 4 bytes.

Bug Fixes:

• [Xtensa] Add spill slot for smaller estimated stack size.
• [Xtensa] Fix wchar type. Previously wchar was internally represented as unsigned char. Now it is represented as signed int.
• [Xtensa] Add absent IR passes. Added common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization.
• [Xtensa] Fix Clang builtins include directory. Fixes #83. Closes #84.
• [LLD][Xtensa] Improve literal sections placement. Literal sections are now put as close as possible to appropriate text sections.
• Get back [Xtensa] Fixes HW loop pass f389074 which was lost during rebase on LLVM 16.0.0. See details about the fix in esp-15.0.0-20230404 release notes.
• [Xtensa] Fix FP mul-sub fusion. Closes #76.
• [Xtensa] Fix asm parsing of special interrupt registers names. Fixes #68. Closes #69
• [Xtensa] Fix i8/i16 alignment. Change preferable alignment for i8 and i16 types on stack to 32-bit.
• [LLD][Xtensa] Recognize bt instruction in lld.
• [Xtensa] Respect srli assembler semantics. Fixes #70.