arcv: apex: Add volatile variants for instructions with side effects.

Introduce "unspec_volatile" to handle APEX instructions that have
side effects and must not be optimized away by the compiler.
When an instruction is defined with the "side_effect" attribute via
preventing optimizations such as common subexpression elimination,
loop-invariant motion, or dead code elimination.

Instructions with no destination register are treated as volatile.

Signed-off-by: Luis Silva <[email protected]>

Author: luismgsilva

gcc/config/riscv/arcv-apex.md

@@ -93,6 +93,21 @@
   [(set_attr "type" "arith,arith")]
 )
 
+;; Used by "XD" insn. format: `insn dest` volatile
+(define_insn "riscv_arcv_apex_dest_volatile"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "xAVpXD")]
+	UNSPEC_ARCV_APEX_DEST))]
+  ""
+{
+  const char *str = arcv_apex_get_insn_name (operands[1]);
+  return xasprintf ("%s\t%s ; 'XD' `insn dest` volatile",
+		    str,
+		    reg_names[REGNO (operands[0])]);
+}
+  [(set_attr "type" "arith")]
+)
+
 ;; Used by "XD" insn. format: `insn dest`
 (define_insn "riscv_arcv_apex_dest_ftype"
   [(set (match_operand:SI 0 "register_operand" "=r")
@@ -108,6 +123,34 @@
   [(set_attr "type" "arith")]
 )
 
+;; Used by "XI","XD" insn. format: `insn dest, src0` volatile
+(define_insn "riscv_arcv_apex_dest_src0_volatile"
+  [(set (match_operand:SI 0 "register_operand" "=r,r")
+	(unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "xAVpXI,xAVpXD")
+		    (match_operand:SI 2 "nonmemory_operand" "I,r")]
+	UNSPEC_ARCV_APEX_DEST_SRC0))]
+  ""
+{
+  const char *str = arcv_apex_get_insn_name (operands[1]);
+  switch (which_alternative)
+  {
+    case 0:
+      return xasprintf ("%si\t%s,%d ; 'XI' `insn des, src0` volatile",
+			str,
+			reg_names[REGNO (operands[0])],
+			(int) INTVAL (operands[2]));
+    case 1:
+      return xasprintf ("%s\t%s,%s ; 'XD' `insn des, src0` volatile",
+			str,
+			reg_names[REGNO (operands[0])],
+			reg_names[REGNO (operands[2])]);
+    default:
+      gcc_unreachable ();
+  }
+}
+  [(set_attr "type" "arith,arith")]
+)
+
 ;; Used by "XI","XD" insn. format: `insn dest, src0`
 (define_insn "riscv_arcv_apex_dest_ftype_src0"
   [(set (match_operand:SI 0 "register_operand" "=r,r")
@@ -136,6 +179,43 @@
   [(set_attr "type" "arith,arith")]
 )
 
+;; Used by "XS","XC","XD" insn. format: `insn dest, src0, imm/src1` volatile
+(define_insn "riscv_arcv_apex_dest_src0_src1_volatile"
+  [(set (match_operand:SI 0 "register_operand" "=r,r,r")
+	(unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "xAVpXS,xAVpXC,xAVpXD")
+		    (match_operand:SI 2 "register_operand" "r,0,r")
+		    (match_operand:SI 3 "nonmemory_operand" "B8,I,r")]
+	UNSPEC_ARCV_APEX_DEST_SRC0_SRC1))]
+  ""
+{
+  const char *str = arcv_apex_get_insn_name (operands[1]);
+  switch (which_alternative)
+  {
+    case 0:
+      return xasprintf ("%si\t%s,%s,%d ; 'XS' `insn dest, src0, imm/src1` volatile",
+			str,
+			reg_names[REGNO (operands[0])],
+			reg_names[REGNO (operands[2])],
+			(int) INTVAL (operands[3]));
+    case 1:
+      return xasprintf ("%s%s\t%s,%s,%d ; 'XC' `insn dest/src0, imm` volatile",
+			str,
+			reg_names[REGNO (operands[0])],
+			reg_names[REGNO (operands[2])],
+			(int) INTVAL (operands[3]));
+    case 2:
+      return xasprintf ("%s\t%s,%s,%s ; 'XD' `insn dest, src0, imm/src1` volatile",
+			str,
+			reg_names[REGNO (operands[0])],
+			reg_names[REGNO (operands[2])],
+			reg_names[REGNO (operands[3])]);
+    default:
+      gcc_unreachable ();
+  }
+}
+  [(set_attr "type" "arith,arith,arith")]
+)
+
 ;; Used by "XS","XC","XD" insn. format: `insn dest, src0, imm/src1`
 (define_insn "riscv_arcv_apex_dest_ftype_src0_src1"
   [(set (match_operand:SI 0 "register_operand" "=r,r,r")

gcc/config/riscv/riscv-builtins.cc

@@ -650,9 +650,9 @@ arcv_apex_resolve_insn_format (unsigned int insn_format, unsigned int opcode)
   if ((insn_format & 0xF) != APEX_NONE)
     return insn_format;
 
-  /* Extract the operand flags (DEST, SRC0, SRC1) from bits 4–6.
+  /* Extract the operand flags (DEST, SRC0, SRC1) from bits 5–7.
      These bits encode the operand signature used for format selection.  */
-  unsigned int insn_operands = insn_format >> 4;
+  unsigned int insn_operands = insn_format >> 5;
 
   /* Assign the most general format APEX_XD.  If opcode does not permit,
      it will report an error at "arcv_apex_validate_insn_format".  */
@@ -784,7 +784,7 @@ arcv_apex_validate_insn_format (const char* fn_name, unsigned int insn_format,
    that corresponds to the instruction variant used during RTL generation.
 
    The operand layout is extracted by right-shifting out APEX_DEST and
-   APEX_SRC flags (bits 4–6).  The function matches the operand pattern
+   APEX_SRC flags (bits 5–7).  The function matches the operand pattern
    against predefined instruction codes for different instruction formats
    such as XI, XS, XC, and XD.
 
@@ -793,7 +793,8 @@ arcv_apex_validate_insn_format (const char* fn_name, unsigned int insn_format,
 static enum insn_code
 arcv_apex_get_icode (unsigned insn_format)
 {
-  unsigned int insn_operands = insn_format >> 4;
+  unsigned int insn_operands = insn_format >> 5;
+  bool is_volatile = insn_format & APEX_VOLATILE;
 
   switch (insn_operands)
   {
@@ -811,15 +812,21 @@ arcv_apex_get_icode (unsigned insn_format)
 
     /* Used by "XD" insn. format: `insn dest`  */
     case APEX_DEST_FTYPE:
-     return CODE_FOR_riscv_arcv_apex_dest_ftype;
+     return is_volatile
+      ? CODE_FOR_riscv_arcv_apex_dest_ftype_v
+      : CODE_FOR_riscv_arcv_apex_dest_ftype;
 
     /* Used by "XI","XD" insn. format: `insn dest, src0`  */
     case APEX_DEST_FTYPE_SRC0:
-      return CODE_FOR_riscv_arcv_apex_dest_ftype_src0;
+      return is_volatile
+      ? CODE_FOR_riscv_arcv_apex_dest_ftype_src0_v
+      : CODE_FOR_riscv_arcv_apex_dest_ftype_src0;
 
     /* Used by "XS","XC","XD" insn. format: `insn dest, src0, imm/src1`  */
     case APEX_DEST_FTYPE_SRC0_SRC1:
-      return CODE_FOR_riscv_arcv_apex_dest_ftype_src0_src1;
+      return is_volatile
+      ? CODE_FOR_riscv_arcv_apex_dest_ftype_src0_src1_v
+      : CODE_FOR_riscv_arcv_apex_dest_ftype_src0_src1;
 
     default:
       /* If none is selected, the default is "CODE_FOR_nothing".  */

gcc/config/riscv/riscv-c.cc

@@ -267,6 +267,8 @@ arcv_apex_pragma_intrinsic (cpp_reader *)
       insn_formats |= APEX_XI;
     else if (strcmp (attribute, "XC") == 0)
       insn_formats |= APEX_XC;
+    else if (strcmp (attribute, "side_effect") == 0)
+      insn_formats |= APEX_VOLATILE;
     else if (strcmp (attribute, "opcode") == 0)
     {
       if (pragma_lex (&x) != CPP_EQ || pragma_lex (&x) != CPP_GREATER)

gcc/config/riscv/riscv.cc

@@ -9688,17 +9688,17 @@ riscv_asm_output_variant_cc (FILE *stream, const tree decl, const char *name)
   more `.extInstruction` lines into the assembly output file, allowing the
   assembler and disassembler to recognize the instruction variants.
 
-  The operand signature is encoded in bits 4–6 of `insn_format` and indicates
+  The operand signature is encoded in bits 5–7 of `insn_format` and indicates
   the presence and types of operands such as destination, source0
   and source1.  */
 
 void
 arcv_apex_print_insn_section (const char *insn_name, int opcode,
 			      unsigned int insn_format)
 {
-  /* Extract the operand flags (DEST, SRC0, SRC1) from bits 4–6.
+  /* Extract the operand flags (DEST, SRC0, SRC1) from bits 5–7.
      These bits encode the operand signature used for format selection.  */
-  unsigned int insn_operands = insn_format >> 4;
+  unsigned int insn_operands = insn_format >> 5;
 
   /* Print XD format line, adding operand info flags if absent.  */
   if (insn_format & APEX_XD)

gcc/config/riscv/riscv.h

@@ -72,9 +72,10 @@ enum apex_insn_format {
   APEX_XS   = 1 << 1,
   APEX_XI   = 1 << 2,
   APEX_XC   = 1 << 3,
-  APEX_DEST = 1 << 4,
-  APEX_SRC0 = 1 << 5,
-  APEX_SRC1 = 1 << 6,
+  APEX_VOLATILE = 1 << 4,
+  APEX_DEST = 1 << 5,
+  APEX_SRC0 = 1 << 6,
+  APEX_SRC1 = 1 << 7,
 };
 
 #endif /* ! RISCV_APEX */