arcv: Add APEX support.

gcc/config/riscv/constraints.md

@@ -355,3 +355,38 @@
 (define_register_constraint "xAVn30" "GENERAL_REGS"
   "Even-odd register pair suitable as a 64-bit operand of some uDSP instructions."
   "regno != 30")
+
+;; ARC-V APEX Constraints
+(define_constraint "B8"
+  "An 8-bit signed immediate (-128 to 127)."
+  (and (match_code "const_int")
+       (match_test "IN_RANGE (ival, -128, 127)")))
+
+;; These constraints check whether the APEX builtin instruction identified by
+;; the given subcode (an integer indexing into `riscv_apex_builtins`) has the
+;; specified instruction format enabled (APEX_XD, APEX_XS, APEX_XI, or APEX_XC).
+;;
+;; The function `arcv_apex_format_supports_p` returns true if the instruction's
+;; supported formats include the queried format.
+;;
+;; This validation is used in instruction selection to ensure the chosen pattern
+;; matches only when the instruction supports the required format.
+(define_constraint "xAVpXD"
+  "Validate support of APEX_XD instruction format."
+  (and (match_code "const_int")
+       (match_test "arcv_apex_format_supports_p (INTVAL (op), APEX_XD)")))
+
+(define_constraint "xAVpXS"
+  "Validate support of APEX_XS instruction format."
+  (and (match_code "const_int")
+       (match_test "arcv_apex_format_supports_p (INTVAL (op), APEX_XS)")))
+
+(define_constraint "xAVpXI"
+  "Validate support of APEX_XI instruction format."
+  (and (match_code "const_int")
+       (match_test "arcv_apex_format_supports_p (INTVAL (op), APEX_XI)")))
+
+(define_constraint "xAVpXC"
+  "Validate support of APEX_XC instruction format."
+  (and (match_code "const_int")
+       (match_test "arcv_apex_format_supports_p (INTVAL (op), APEX_XC)")))

gcc/config/riscv/iterators.md

@@ -22,6 +22,12 @@
 ;; Mode Iterators
 ;; -------------------------------------------------------------------
 
+;; These mode iterators are used by ARCV APEX to generate
+;; all valid combinations of operand types.
+(define_mode_iterator DM  [SI DI SF DF])   ;; dest
+(define_mode_iterator S0M [SI DI SF DF])   ;; src0
+(define_mode_iterator S1M [SI DI SF DF])   ;; src1
+
 ;; This mode iterator allows 32-bit and 64-bit GPR patterns to be generated
 ;; from the same template.
 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])