docs: align atomix ordering contracts#13
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Signed-off-by: Robin He <git@hybscloud.com>
Signed-off-by: Robin He <git@hybscloud.com>
Signed-off-by: Robin He <git@hybscloud.com>
Signed-off-by: Robin He <git@hybscloud.com>
Signed-off-by: Robin He <git@hybscloud.com>
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Pull request overview
This PR aligns Atomix’s public documentation and internal commentary with the currently implemented memory-ordering and return-value contracts, especially around default Relaxed Load/Store behavior, explicit Acquire/Release edges, and 128-bit limitations on weak architectures. It also updates CI and build tooling timeouts.
Changes:
- Clarify ordering semantics vs
sync/atomic, including default Relaxed Load/Store and explicit Acquire/Release synchronization edges. - Document return-value differences between wrapper APIs, pointer-based 32/64/uintptr APIs, and pointer-based 128-bit Add APIs.
- Document weak-architecture (riscv64/loong64) 128-bit limitations, including non-relaxed Swap aliasing relaxed swap, and update CI/Makefile timeouts.
Reviewed changes
Copilot reviewed 22 out of 22 changed files in this pull request and generated 8 comments.
Show a summary per file
| File | Description |
|---|---|
| uint128.go | Adds notes about riscv64/loong64 128-bit Swap* orderings aliasing relaxed swap. |
| int128.go | Mirrors 128-bit Swap* aliasing notes for signed wrapper. |
| order_uint128.go | Documents MemoryOrder SwapUint128 aliasing on riscv64/loong64. |
| order_int128.go | Documents MemoryOrder SwapInt128 aliasing on riscv64/loong64. |
| internal/arch/stubs_riscv64.go | Updates riscv64 stub docs to reflect low-word LR/SC emulation and Swap128 aliasing. |
| internal/arch/stubs_loong64.go | Updates loong64 stub docs to reflect low-word LL/SC emulation and Swap128 aliasing. |
| internal/arch/asm_riscv64.s | Updates comments describing non-atomic full-width 128-bit emulation. |
| internal/arch/doc.go | Updates internal arch package docs for ordering/fallback and 128-bit caveats. |
| internal/arch/arch_test.go | Updates test comments to match Atomix-specific return-value contract language. |
| order_test.go | Updates pointer-API Add test comment to Atomix contract phrasing. |
| atomix_test.go | Updates wrapper Add/Sub test comments to Atomix contract phrasing. |
| coverage_test.go | Updates wrapper Add/Sub test comments to Atomix contract phrasing. |
| doc.go | Updates package GoDoc: ordering contract, return-value semantics, platform notes, and 128-bit caveats. |
| intrinsics.md | Refines intrinsics documentation (supported coverage, return-value notes, ARM64 ordering limitations). |
| README.md | Updates English README for ordering contract, return values, ARM64 baseline notes, and 128-bit caveats. |
| README.zh-CN.md | Same as README.md for Chinese translation. |
| README.ja.md | Same as README.md for Japanese translation. |
| README.fr.md | Same as README.md for French translation. |
| README.es.md | Same as README.md for Spanish translation. |
| Makefile | Adds go test timeouts for test/bench targets. |
| .github/workflows/ci.yml | Adds workflow permissions/concurrency, job timeouts, Go version patterns, and test timeout. |
| .github/instructions/copilot.instructions.md | Updates contributor guidance to prefer code/docs truth and clarifies contracts/caveats. |
Signed-off-by: Robin He <git@hybscloud.com>
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Summary
Align atomix documentation, repository validation, and test commentary with the implemented memory-ordering contract. The package behavior stays unchanged while public docs distinguish
sync/atomicsequential consistency, atomix explicit ordering, pointer-based 128-bit Add return values, ARM64 intrinsic coverage, and weak-architecture 128-bit limitations.Changes
Public contracts
sync/atomicoperations are sequentially consistent, while atomix defaults Load and Store to Relaxed and requires explicit Acquire/Release edges when synchronization is needed.MemoryOrder.AddInt128andMemoryOrder.AddUint128return old values.Weak-architecture 128-bit caveats
Tooling and tests