Final project created for the course Digital logic design at Politecnico di Milano.
It was also part of the final examination projects for the BSc in Computer Science and Engineering.
The project requirements can be found here.
The documentation for the project can be found here.
This solution achieved the maximum grade of 30 Cum Laude/30.
- VHDL (VHSIC Hardware Description Language)
- Xilinx Vivado v.2022.1