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[csrng/rtl] Remove four prim_fifo_sync from the data path #28428

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[csrng/rtl] Remove four prim_fifo_sync from the data path #28428

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f35aaa0
[csrng] Version bump to 3.0.0
glaserf Oct 6, 2025
c05e0ac
[csrng/rtl] Simplify main state machine
glaserf Oct 3, 2025
ca56987
[csrng/rtl] Remove the cmdreq FIFO from ctr_drbg_cmd
glaserf Aug 27, 2025
5e4fcaf
[csrng/rtl] Remove the pdata FIFO from ctr_drbg_upd
glaserf Sep 8, 2025
266861f
[csrng/rtl] Remove the bencreq FIFO from ctr_drbg_upd
glaserf Sep 8, 2025
8d9ab6b
[csrng/rtl] Remove the updreq FIFO from ctr_drbg_upd
glaserf Oct 6, 2025
89786d4
[csrng] Use the correct counter widths in csrng_err_vseq
glaserf Oct 7, 2025
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46 changes: 5 additions & 41 deletions hw/ip/csrng/data/csrng.hjson
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -20,10 +20,10 @@
dv_doc: "../doc/dv",
hw_checklist: "../doc/checklist",
sw_checklist: "/sw/device/lib/dif/dif_csrng",
version: "2.0.0",
version: "3.0.0",
life_stage: "L1",
design_stage: "D2S",
verification_stage: "V2S",
design_stage: "D1",
verification_stage: "V1",
dif_stage: "S2",
clocking: [{clock: "clk_i", reset: "rst_ni"}],
bus_interfaces: [
Expand Down Expand Up @@ -728,15 +728,6 @@
This bit will stay set until the next reset.
'''
}
{ bits: "2",
name: "SFIFO_CMDREQ_ERR",
desc: '''
This bit will be set to one when an error has been detected for the
cmdreq FIFO. The type of error is reflected in the type status
bits (bits 28 through 30 of this register).
This bit will stay set until the next reset.
'''
}
{ bits: "3",
name: "SFIFO_RCSTAGE_ERR",
desc: '''
Expand All @@ -755,24 +746,6 @@
This bit will stay set until the next reset.
'''
}
{ bits: "5",
name: "SFIFO_UPDREQ_ERR",
desc: '''
This bit will be set to one when an error has been detected for the
updreq FIFO. The type of error is reflected in the type status
bits (bits 28 through 30 of this register).
This bit will stay set until the next reset.
'''
}
{ bits: "6",
name: "SFIFO_BENCREQ_ERR",
desc: '''
This bit will be set to one when an error has been detected for the
bencreq FIFO. The type of error is reflected in the type status
bits (bits 28 through 30 of this register).
This bit will stay set until the next reset.
'''
}
{ bits: "7",
name: "SFIFO_BENCACK_ERR",
desc: '''
Expand All @@ -782,15 +755,6 @@
This bit will stay set until the next reset.
'''
}
{ bits: "8",
name: "SFIFO_PDATA_ERR",
desc: '''
This bit will be set to one when an error has been detected for the
pdata FIFO. The type of error is reflected in the type status
bits (bits 28 through 30 of this register).
This bit will stay set until the next reset.
'''
}
{ bits: "9",
name: "SFIFO_FINAL_ERR",
desc: '''
Expand Down Expand Up @@ -975,12 +939,12 @@
swaccess: "ro",
hwaccess: "hwo",
fields: [
{ bits: "7:0",
{ bits: "5:0",
name: "MAIN_SM_STATE",
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Can you please grep for MAIN_SM_STATE in the repo and see if there is still software reading this register for properly using CSRNG? I am sure we did this in the past, but I am not sure if this software is run in CI. It might just get run in the nightly / weekly regressions.

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Sure, good point! The only thing I could find was a HAL function in the CSRNG dif and a call to in the the dif unit test.
However, the expected value of '42' (hex 0x2A) there does not match the old reset value, and the unit test just after this one, which reads the HW exception status register, also expects 42, so I lean towards the option that this test does not expect the actual reset value of the hardware but just tests the dif itself?

desc: '''This is the state of the CSRNG main state machine.
See the RTL file `csrng_main_sm` for the meaning of the values.
'''
resval: 0x4e
resval: 0x37
}
]
},
Expand Down
45 changes: 10 additions & 35 deletions hw/ip/csrng/doc/registers.md
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Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -555,12 +555,12 @@ Writing a zero resets this status bit.
Hardware detection of error conditions status register
- Offset: `0x54`
- Reset default: `0x0`
- Reset mask: `0x77f0ffff`
- Reset mask: `0x77f0fe9b`

### Fields

```wavejson
{"reg": [{"name": "SFIFO_CMD_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GENBITS_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_CMDREQ_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_RCSTAGE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_KEYVRC_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_UPDREQ_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_BENCREQ_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_BENCACK_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_PDATA_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_FINAL_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GBENCACK_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GRCSTAGE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GGENREQ_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GADSTAGE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GGENBITS_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_CMDID_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 4}, {"name": "CMD_STAGE_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "MAIN_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_GEN_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_UPDBE_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_UPDOB_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "AES_CIPHER_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CMD_GEN_CNT_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}, {"name": "FIFO_WRITE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FIFO_READ_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FIFO_STATE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}}
{"reg": [{"name": "SFIFO_CMD_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GENBITS_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}, {"name": "SFIFO_RCSTAGE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_KEYVRC_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 2}, {"name": "SFIFO_BENCACK_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}, {"name": "SFIFO_FINAL_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GBENCACK_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GRCSTAGE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GGENREQ_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GADSTAGE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GGENBITS_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_CMDID_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 4}, {"name": "CMD_STAGE_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "MAIN_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_GEN_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_UPDBE_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_UPDOB_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "AES_CIPHER_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CMD_GEN_CNT_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}, {"name": "FIFO_WRITE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FIFO_READ_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FIFO_STATE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}}
```

| Bits | Type | Reset | Name |
Expand All @@ -585,13 +585,12 @@ Hardware detection of error conditions status register
| 11 | ro | 0x0 | [SFIFO_GRCSTAGE_ERR](#err_code--sfifo_grcstage_err) |
| 10 | ro | 0x0 | [SFIFO_GBENCACK_ERR](#err_code--sfifo_gbencack_err) |
| 9 | ro | 0x0 | [SFIFO_FINAL_ERR](#err_code--sfifo_final_err) |
| 8 | ro | 0x0 | [SFIFO_PDATA_ERR](#err_code--sfifo_pdata_err) |
| 8 | | | Reserved |
| 7 | ro | 0x0 | [SFIFO_BENCACK_ERR](#err_code--sfifo_bencack_err) |
| 6 | ro | 0x0 | [SFIFO_BENCREQ_ERR](#err_code--sfifo_bencreq_err) |
| 5 | ro | 0x0 | [SFIFO_UPDREQ_ERR](#err_code--sfifo_updreq_err) |
| 6:5 | | | Reserved |
| 4 | ro | 0x0 | [SFIFO_KEYVRC_ERR](#err_code--sfifo_keyvrc_err) |
| 3 | ro | 0x0 | [SFIFO_RCSTAGE_ERR](#err_code--sfifo_rcstage_err) |
| 2 | ro | 0x0 | [SFIFO_CMDREQ_ERR](#err_code--sfifo_cmdreq_err) |
| 2 | | | Reserved |
| 1 | ro | 0x0 | [SFIFO_GENBITS_ERR](#err_code--sfifo_genbits_err) |
| 0 | ro | 0x0 | [SFIFO_CMD_ERR](#err_code--sfifo_cmd_err) |

Expand Down Expand Up @@ -698,30 +697,12 @@ final FIFO. The type of error is reflected in the type status
bits (bits 28 through 30 of this register).
This bit will stay set until the next reset.

### ERR_CODE . SFIFO_PDATA_ERR
This bit will be set to one when an error has been detected for the
pdata FIFO. The type of error is reflected in the type status
bits (bits 28 through 30 of this register).
This bit will stay set until the next reset.

### ERR_CODE . SFIFO_BENCACK_ERR
This bit will be set to one when an error has been detected for the
bencack FIFO. The type of error is reflected in the type status
bits (bits 28 through 30 of this register).
This bit will stay set until the next reset.

### ERR_CODE . SFIFO_BENCREQ_ERR
This bit will be set to one when an error has been detected for the
bencreq FIFO. The type of error is reflected in the type status
bits (bits 28 through 30 of this register).
This bit will stay set until the next reset.

### ERR_CODE . SFIFO_UPDREQ_ERR
This bit will be set to one when an error has been detected for the
updreq FIFO. The type of error is reflected in the type status
bits (bits 28 through 30 of this register).
This bit will stay set until the next reset.

### ERR_CODE . SFIFO_KEYVRC_ERR
This bit will be set to one when an error has been detected for the
keyvrc FIFO. The type of error is reflected in the type status
Expand All @@ -734,12 +715,6 @@ rcstage FIFO. The type of error is reflected in the type status
bits (bits 28 through 30 of this register).
This bit will stay set until the next reset.

### ERR_CODE . SFIFO_CMDREQ_ERR
This bit will be set to one when an error has been detected for the
cmdreq FIFO. The type of error is reflected in the type status
bits (bits 28 through 30 of this register).
This bit will stay set until the next reset.

### ERR_CODE . SFIFO_GENBITS_ERR
This bit will be set to one when an error has been detected for the
command stage genbits FIFO. The type of error is reflected in the type status
Expand Down Expand Up @@ -781,19 +756,19 @@ an interrupt or an alert.
## MAIN_SM_STATE
Main state machine state debug register
- Offset: `0x5c`
- Reset default: `0x4e`
- Reset mask: `0xff`
- Reset default: `0x37`
- Reset mask: `0x3f`

### Fields

```wavejson
{"reg": [{"name": "MAIN_SM_STATE", "bits": 8, "attr": ["ro"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
{"reg": [{"name": "MAIN_SM_STATE", "bits": 6, "attr": ["ro"], "rotate": -90}, {"bits": 26}], "config": {"lanes": 1, "fontsize": 10, "vspace": 150}}
```

| Bits | Type | Reset | Name | Description |
|:------:|:------:|:-------:|:--------------|:-------------------------------------------------------------------------------------------------------------------|
| 31:8 | | | | Reserved |
| 7:0 | ro | 0x4e | MAIN_SM_STATE | This is the state of the CSRNG main state machine. See the RTL file `csrng_main_sm` for the meaning of the values. |
| 31:6 | | | | Reserved |
| 5:0 | ro | 0x37 | MAIN_SM_STATE | This is the state of the CSRNG main state machine. See the RTL file `csrng_main_sm` for the meaning of the values. |


<!-- END CMDGEN -->
20 changes: 0 additions & 20 deletions hw/ip/csrng/dv/env/csrng_env_pkg.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -56,13 +56,9 @@ package csrng_env_pkg;
typedef enum int {
sfifo_cmd_error = 0,
sfifo_genbits_error = 1,
sfifo_cmdreq_error = 2,
sfifo_rcstage_error = 3,
sfifo_keyvrc_error = 4,
sfifo_updreq_error = 5,
sfifo_bencreq_error = 6,
sfifo_bencack_error = 7,
sfifo_pdata_error = 8,
sfifo_final_error = 9,
sfifo_gbencack_error = 10,
sfifo_grcstage_error = 11,
Expand All @@ -86,13 +82,9 @@ package csrng_env_pkg;
// ERR_CODE
sfifo_cmd_err = 0,
sfifo_genbits_err = 1,
sfifo_cmdreq_err = 2,
sfifo_rcstage_err = 3,
sfifo_keyvrc_err = 4,
sfifo_updreq_err = 5,
sfifo_bencreq_err = 6,
sfifo_bencack_err = 7,
sfifo_pdata_err = 8,
sfifo_final_err = 9,
sfifo_gbencack_err = 10,
sfifo_grcstage_err = 11,
Expand All @@ -113,13 +105,9 @@ package csrng_env_pkg;
// ERR_CODE_TEST
sfifo_cmd_err_test = 26,
sfifo_genbits_err_test = 27,
sfifo_cmdreq_err_test = 28,
sfifo_rcstage_err_test = 29,
sfifo_keyvrc_err_test = 30,
sfifo_updreq_err_test = 31,
sfifo_bencreq_err_test = 32,
sfifo_bencack_err_test = 33,
sfifo_pdata_err_test = 34,
sfifo_final_err_test = 35,
sfifo_gbencack_err_test = 36,
sfifo_grcstage_err_test = 37,
Expand All @@ -142,13 +130,9 @@ package csrng_env_pkg;
typedef enum int {
SFIFO_CMD_ERR = 0,
SFIFO_GENBITS_ERR = 1,
SFIFO_CMDREQ_ERR = 2,
SFIFO_RCSTAGE_ERR = 3,
SFIFO_KEYVRC_ERR = 4,
SFIFO_UPDREQ_ERR = 5,
SFIFO_BENCREQ_ERR = 6,
SFIFO_BENCACK_ERR = 7,
SFIFO_PDATA_ERR = 8,
SFIFO_FINAL_ERR = 9,
SFIFO_GBENCACK_ERR = 10,
SFIFO_GRCSTAGE_ERR = 11,
Expand Down Expand Up @@ -187,13 +171,9 @@ package csrng_env_pkg;
sfifo_grcstage = 4,
sfifo_gbencack = 5,
sfifo_final = 6,
sfifo_pdata = 7,
sfifo_bencack = 8,
sfifo_bencreq = 9,
sfifo_updreq = 10,
sfifo_keyvrc = 11,
sfifo_rcstage = 12,
sfifo_cmdreq = 13,
sfifo_genbits = 14,
sfifo_cmd = 15
} which_fifo_e;
Expand Down
6 changes: 3 additions & 3 deletions hw/ip/csrng/dv/env/csrng_path_if.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -17,15 +17,15 @@ interface csrng_path_if
case (fifo_name) inside
"sfifo_cmd", "sfifo_genbits": return {core_path, $sformatf(".gen_cmd_stage[%0d]", app),
".u_csrng_cmd_stage.", fifo_name, "_", which_path};
"sfifo_cmdreq", "sfifo_rcstage", "sfifo_keyvrc": return {core_path, ".u_csrng_ctr_drbg_cmd.",
"sfifo_rcstage", "sfifo_keyvrc": return {core_path, ".u_csrng_ctr_drbg_cmd.",
fifo_name, "_", which_path};
"sfifo_updreq", "sfifo_bencreq", "sfifo_bencack", "sfifo_pdata", "sfifo_final": return
"sfifo_bencack", "sfifo_final": return
{core_path, ".u_csrng_ctr_drbg_upd.", fifo_name, "_", which_path};
"sfifo_gbencack", "sfifo_grcstage", "sfifo_ggenreq", "sfifo_gadstage", "sfifo_ggenbits":
return {core_path,".u_csrng_ctr_drbg_gen.sfifo_", fifo_name.substr(7, fifo_name.len()-1),
"_", which_path};
"sfifo_cmdid": return {core_path, ".u_csrng_block_encrypt.", fifo_name, "_", which_path};
default: `uvm_fatal("csrng_path_if", "Invalid fifo name!")
default: `uvm_fatal("csrng_path_if", $sformatf("%s: Invalid fifo name!", fifo_name))
endcase // case (fifo_name.substr(6, fifo_name.len()-1))
endfunction // fifo_err_path

Expand Down
28 changes: 13 additions & 15 deletions hw/ip/csrng/dv/env/seq_lib/csrng_err_vseq.sv
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Expand Up @@ -99,10 +99,10 @@ class csrng_err_vseq extends csrng_base_vseq;
cfg.which_app_err_alert, fld_name), UVM_MEDIUM)

case (cfg.which_err_code) inside
sfifo_cmd_err, sfifo_genbits_err, sfifo_cmdreq_err, sfifo_rcstage_err, sfifo_keyvrc_err,
sfifo_bencreq_err, sfifo_final_err, sfifo_gbencack_err, sfifo_grcstage_err,
sfifo_gadstage_err, sfifo_ggenbits_err, sfifo_cmdid_err, sfifo_updreq_err,
sfifo_bencack_err, sfifo_pdata_err, sfifo_ggenreq_err: begin
sfifo_cmd_err, sfifo_genbits_err, sfifo_rcstage_err, sfifo_keyvrc_err,
sfifo_final_err, sfifo_gbencack_err, sfifo_grcstage_err,
sfifo_gadstage_err, sfifo_ggenbits_err, sfifo_cmdid_err,
sfifo_bencack_err, sfifo_ggenreq_err: begin
fld = csr.get_field_by_name(fld_name);
fifo_base_path = fld_name.substr(0, last_index-1);

Expand All @@ -114,8 +114,8 @@ class csrng_err_vseq extends csrng_base_vseq;
`uvm_info(`gfn, $sformatf("Forcing this FIFO error type %s", cfg.which_fifo_err.name()),
UVM_MEDIUM)

if (cfg.which_err_code == sfifo_updreq_err || cfg.which_err_code == sfifo_bencack_err ||
cfg.which_err_code == sfifo_pdata_err || cfg.which_err_code == sfifo_ggenreq_err) begin
if (cfg.which_err_code == sfifo_ggenreq_err ||
cfg.which_err_code == sfifo_bencack_err) begin
force_all_fifo_errs_exception(fifo_forced_paths, fifo_forced_values, path_exts, fld,
1'b1, cfg.which_fifo_err);

Expand Down Expand Up @@ -221,17 +221,17 @@ class csrng_err_vseq extends csrng_base_vseq;
cmd_gen_cnt_sel: begin
fld = csr.get_field_by_name(fld_name);
path = cfg.csrng_path_vif.cmd_gen_cnt_err_path(cfg.which_app_err_alert);
force_cnt_err(path, fld, 1'b1, 13);
force_cnt_err(path, fld, 1'b1, csrng_pkg::GenBitsCtrWidth);
end
drbg_upd_cnt_sel: begin
fld = csr.get_field_by_name(fld_name);
path = cfg.csrng_path_vif.drbg_upd_cnt_err_path();
force_cnt_err(path, fld, 1'b1, 32);
force_cnt_err(path, fld, 1'b1, csrng_pkg::CtrLen);
end
drbg_gen_cnt_sel: begin
fld = csr.get_field_by_name(fld_name);
path = cfg.csrng_path_vif.drbg_gen_cnt_err_path();
force_cnt_err(path, fld, 1'b1, 32);
force_cnt_err(path, fld, 1'b1, csrng_pkg::CtrLen);
end
endcase
csr_rd(.ptr(ral.err_code), .value(backdoor_err_code_val));
Expand Down Expand Up @@ -263,9 +263,7 @@ class csrng_err_vseq extends csrng_base_vseq;
value2 = fifo_err_value[1][path_key];

if (cfg.which_err_code == fifo_read_error &&
((cfg.which_fifo == sfifo_ggenreq) || (cfg.which_fifo == sfifo_pdata) ||
(cfg.which_fifo == sfifo_bencack) || (cfg.which_fifo == sfifo_updreq)))
begin
((cfg.which_fifo == sfifo_ggenreq) || (cfg.which_fifo == sfifo_bencack))) begin
force_fifo_err_exception(path1, path2, 1'b1, 1'b0, 1'b0, fld, 1'b1);

// For sfifo_gadstage the down stream FIFO also takes inputs from sources other than
Expand Down Expand Up @@ -303,9 +301,9 @@ class csrng_err_vseq extends csrng_base_vseq;
csr_rd(.ptr(ral.err_code), .value(backdoor_err_code_val));
cov_vif.cg_err_code_sample(.err_code(backdoor_err_code_val));
end
sfifo_cmd_err_test, sfifo_genbits_err_test, sfifo_cmdreq_err_test, sfifo_rcstage_err_test,
sfifo_keyvrc_err_test, sfifo_updreq_err_test, sfifo_bencreq_err_test, sfifo_bencack_err_test,
sfifo_pdata_err_test, sfifo_final_err_test, sfifo_gbencack_err_test, sfifo_grcstage_err_test,
sfifo_cmd_err_test, sfifo_genbits_err_test, sfifo_rcstage_err_test,
sfifo_keyvrc_err_test, sfifo_bencack_err_test,
sfifo_final_err_test, sfifo_gbencack_err_test, sfifo_grcstage_err_test,
sfifo_ggenreq_err_test, sfifo_gadstage_err_test, sfifo_ggenbits_err_test,
sfifo_cmdid_err_test, cmd_stage_sm_err_test, main_sm_err_test, drbg_gen_sm_err_test,
drbg_updbe_sm_err_test, drbg_updob_sm_err_test, aes_cipher_sm_err_test, cmd_gen_cnt_err_test,
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