[tlgen] Relax xbar contraints to allow generating non-pow2 matchers

hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson

@@ -3886,7 +3886,7 @@
           data_intg_passthru: "true"
           exec: True
           byte_write: True
-          size: 0x40000000
+          size: 0x80000000
         }
       }
       clock_connections:
@@ -12370,7 +12370,7 @@
               {
                 hart: 0x40000000
               }
-              size_byte: 0x40000000
+              size_byte: 0x80000000
             }
           ]
           xbar: false

hw/top_darjeeling/data/top_darjeeling.hjson

@@ -632,7 +632,7 @@
           data_intg_passthru: "true",
           exec: "True",
           byte_write: "True",
-          size: "0x40000000",
+          size: "0x80000000",
         }
       }
     },

hw/top_darjeeling/dv/autogen/xbar_env_pkg__params.sv

@@ -29,7 +29,7 @@ tl_device_t xbar_devices[$] = '{
         '{32'h22030000, 32'h2203000f}
     }},
     '{"soc_proxy__ctn", '{
-        '{32'h40000000, 32'h7fffffff}
+        '{32'h40000000, 32'hbfffffff}
     }},
     '{"hmac", '{
         '{32'h21110000, 32'h21111fff}

hw/top_darjeeling/ip/xbar_main/data/autogen/xbar_main.gen.hjson

@@ -407,7 +407,7 @@
           {
             hart: 0x40000000
           }
-          size_byte: 0x40000000
+          size_byte: 0x80000000
         }
       ]
       xbar: false

hw/top_darjeeling/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv

@@ -32,7 +32,7 @@ tl_device_t xbar_devices[$] = '{
         '{32'h22030000, 32'h2203000f}
     }},
     '{"soc_proxy__ctn", '{
-        '{32'h40000000, 32'h7fffffff}
+        '{32'h40000000, 32'hbfffffff}
     }},
     '{"hmac", '{
         '{32'h21110000, 32'h21111fff}

hw/top_darjeeling/ip/xbar_main/rtl/autogen/tl_main_pkg.sv

@@ -54,7 +54,7 @@ package tl_main_pkg;
     32'h 007fffff
   };
   localparam logic [31:0] ADDR_MASK_SOC_PROXY__CORE      = 32'h 0000000f;
-  localparam logic [31:0] ADDR_MASK_SOC_PROXY__CTN       = 32'h 3fffffff;
+  localparam logic [31:0] ADDR_SIZE_SOC_PROXY__CTN       = 32'h 80000000;
   localparam logic [31:0] ADDR_MASK_HMAC                 = 32'h 00001fff;
   localparam logic [31:0] ADDR_MASK_KMAC                 = 32'h 00000fff;
   localparam logic [31:0] ADDR_MASK_AES                  = 32'h 000000ff;

hw/top_darjeeling/ip/xbar_main/rtl/autogen/xbar_main.sv

@@ -1188,8 +1188,8 @@ module xbar_main (
                   ~(ADDR_MASK_SRAM_CTRL_MAIN__RAM)) == ADDR_SPACE_SRAM_CTRL_MAIN__RAM) begin
       dev_sel_s1n_49 = 3'd3;
 
-    end else if ((tl_s1n_49_us_h2d.a_address &
-                  ~(ADDR_MASK_SOC_PROXY__CTN)) == ADDR_SPACE_SOC_PROXY__CTN) begin
+    end else if (((tl_s1n_49_us_h2d.a_address < (ADDR_SPACE_SOC_PROXY__CTN + ADDR_SIZE_SOC_PROXY__CTN)) &&
+       (tl_s1n_49_us_h2d.a_address >= ADDR_SPACE_SOC_PROXY__CTN))) begin
       dev_sel_s1n_49 = 3'd4;
 end
   end
@@ -1285,8 +1285,8 @@ end
                   ~(ADDR_MASK_SRAM_CTRL_MBOX__REGS)) == ADDR_SPACE_SRAM_CTRL_MBOX__REGS) begin
       dev_sel_s1n_55 = 6'd21;
 
-    end else if ((tl_s1n_55_us_h2d.a_address &
-                  ~(ADDR_MASK_SOC_PROXY__CTN)) == ADDR_SPACE_SOC_PROXY__CTN) begin
+    end else if (((tl_s1n_55_us_h2d.a_address < (ADDR_SPACE_SOC_PROXY__CTN + ADDR_SIZE_SOC_PROXY__CTN)) &&
+       (tl_s1n_55_us_h2d.a_address >= ADDR_SPACE_SOC_PROXY__CTN))) begin
       dev_sel_s1n_55 = 6'd22;
 
     end else if ((tl_s1n_55_us_h2d.a_address &
@@ -1430,8 +1430,8 @@ end
                   ~(ADDR_MASK_SRAM_CTRL_MBOX__REGS)) == ADDR_SPACE_SRAM_CTRL_MBOX__REGS) begin
       dev_sel_s1n_87 = 6'd21;
 
-    end else if ((tl_s1n_87_us_h2d.a_address &
-                  ~(ADDR_MASK_SOC_PROXY__CTN)) == ADDR_SPACE_SOC_PROXY__CTN) begin
+    end else if (((tl_s1n_87_us_h2d.a_address < (ADDR_SPACE_SOC_PROXY__CTN + ADDR_SIZE_SOC_PROXY__CTN)) &&
+       (tl_s1n_87_us_h2d.a_address >= ADDR_SPACE_SOC_PROXY__CTN))) begin
       dev_sel_s1n_87 = 6'd22;
 
     end else if ((tl_s1n_87_us_h2d.a_address &
@@ -1515,8 +1515,8 @@ end
                   ~(ADDR_MASK_KMAC)) == ADDR_SPACE_KMAC) begin
       dev_sel_s1n_88 = 4'd6;
 
-    end else if ((tl_s1n_88_us_h2d.a_address &
-                  ~(ADDR_MASK_SOC_PROXY__CTN)) == ADDR_SPACE_SOC_PROXY__CTN) begin
+    end else if (((tl_s1n_88_us_h2d.a_address < (ADDR_SPACE_SOC_PROXY__CTN + ADDR_SIZE_SOC_PROXY__CTN)) &&
+       (tl_s1n_88_us_h2d.a_address >= ADDR_SPACE_SOC_PROXY__CTN))) begin
       dev_sel_s1n_88 = 4'd7;
 
     end else if ((tl_s1n_88_us_h2d.a_address &

hw/top_darjeeling/lint/top_darjeeling.waiver

@@ -77,3 +77,6 @@ waive -rules {LINE_LENGTH} -location {top_darjeeling.sv} -regexp {Line length of
 
 waive -rules LINE_LENGTH -location {top_darjeeling_rnd_cnst_pkg.sv} -regexp {Line length of [0-9]+ exceeds 100 character limit} \
       -comment "top_darjeeling_rnd_cnst_pkg is auto-generated and adhering to the line length limit is not always feasible for auto-generated code"
+
+waive -rules {LINE_LENGTH} -location {xbar_main.sv} -regexp {Line length of [0-9]+ exceeds 100 character limit} \
+      -comment "xbar_main is auto-generated and adhering to the line length limit is not always feasible for auto-generated code"

hw/top_darjeeling/rtl/autogen/top_darjeeling_pkg.sv

@@ -187,7 +187,7 @@ package top_darjeeling_pkg;
   /**
    * Peripheral size in bytes for ctn device on soc_proxy in top darjeeling.
    */
-  parameter int unsigned TOP_DARJEELING_SOC_PROXY_CTN_SIZE_BYTES = 32'h40000000;
+  parameter int unsigned TOP_DARJEELING_SOC_PROXY_CTN_SIZE_BYTES = 32'h80000000;
 
   /**
    * Peripheral base address for regs device on sram_ctrl_ret_aon in top darjeeling.
@@ -547,7 +547,7 @@ package top_darjeeling_pkg;
   /**
    * Memory size for ctn in top darjeeling.
    */
-  parameter int unsigned TOP_DARJEELING_CTN_SIZE_BYTES = 32'h40000000;
+  parameter int unsigned TOP_DARJEELING_CTN_SIZE_BYTES = 32'h80000000;
 
   /**
   * Memory base address for ram_ctn in top darjeeling.

hw/top_darjeeling/sw/autogen/chip/top_darjeeling.rs

@@ -271,7 +271,7 @@ pub const SOC_PROXY_CTN_BASE_ADDR: usize = 0x40000000;
 /// memory-mapped registers associated with this peripheral should have an
 /// address between #SOC_PROXY_CTN_BASE_ADDR and
 /// `SOC_PROXY_CTN_BASE_ADDR + SOC_PROXY_CTN_SIZE_BYTES`.
-pub const SOC_PROXY_CTN_SIZE_BYTES: usize = 0x40000000;
+pub const SOC_PROXY_CTN_SIZE_BYTES: usize = 0x80000000;
 
 /// Peripheral base address for regs device on sram_ctrl_ret_aon in top darjeeling.
 ///
@@ -767,7 +767,7 @@ pub const RV_CORE_IBEX_CFG_SIZE_BYTES: usize = 0x800;
 pub const CTN_BASE_ADDR: usize = 0x40000000;
 
 /// Memory size for ctn in top darjeeling.
-pub const CTN_SIZE_BYTES: usize = 0x40000000;
+pub const CTN_SIZE_BYTES: usize = 0x80000000;
 
 /// Memory base address for ram_ret_aon in top darjeeling.
 pub const RAM_RET_AON_BASE_ADDR: usize = 0x30600000;

hw/top_darjeeling/sw/autogen/top_darjeeling.h

@@ -352,7 +352,7 @@ extern "C" {
  * address between #TOP_DARJEELING_SOC_PROXY_CTN_BASE_ADDR and
  * `TOP_DARJEELING_SOC_PROXY_CTN_BASE_ADDR + TOP_DARJEELING_SOC_PROXY_CTN_SIZE_BYTES`.
  */
-#define TOP_DARJEELING_SOC_PROXY_CTN_SIZE_BYTES 0x40000000u
+#define TOP_DARJEELING_SOC_PROXY_CTN_SIZE_BYTES 0x80000000u
 
 /**
  * Peripheral base address for regs device on sram_ctrl_ret_aon in top darjeeling.
@@ -993,7 +993,7 @@ extern "C" {
 /**
  * Memory size for ctn in top darjeeling.
  */
-#define TOP_DARJEELING_CTN_SIZE_BYTES 0x40000000u
+#define TOP_DARJEELING_CTN_SIZE_BYTES 0x80000000u
 
 /**
  * Memory base address for ram_ret_aon in top darjeeling.

hw/top_darjeeling/sw/autogen/top_darjeeling_memory.h

@@ -32,7 +32,7 @@
 /**
  * Memory size for soc_proxy_ctn in top darjeeling.
  */
-#define TOP_DARJEELING_CTN_SIZE_BYTES 0x40000000
+#define TOP_DARJEELING_CTN_SIZE_BYTES 0x80000000
 
 /**
  * Memory base for sram_ctrl_ret_aon_ram_ret_aon in top darjeeling.
@@ -391,7 +391,7 @@
  * address between #TOP_DARJEELING_SOC_PROXY_CTN_BASE_ADDR and
  * `TOP_DARJEELING_SOC_PROXY_CTN_BASE_ADDR + TOP_DARJEELING_SOC_PROXY_CTN_SIZE_BYTES`.
  */
-#define TOP_DARJEELING_SOC_PROXY_CTN_SIZE_BYTES 0x40000000
+#define TOP_DARJEELING_SOC_PROXY_CTN_SIZE_BYTES 0x80000000
 /**
  * Peripheral base address for regs device on sram_ctrl_ret_aon in top darjeeling.
  *

hw/top_darjeeling/sw/autogen/top_darjeeling_memory.ld

@@ -14,7 +14,7 @@
  * address for whichever half of the flash contains the corresponding boot stage.
  */
 MEMORY {
-  ctn(rwx) : ORIGIN = 0x40000000, LENGTH = 0x40000000
+  ctn(rwx) : ORIGIN = 0x40000000, LENGTH = 0x80000000
   ram_ret_aon(rwx) : ORIGIN = 0x30600000, LENGTH = 0x1000
   ram_main(rwx) : ORIGIN = 0x10000000, LENGTH = 0x10000
   ram_mbox(rwx) : ORIGIN = 0x11000000, LENGTH = 0x1000

util/tlgen/lib.py

@@ -199,7 +199,8 @@ def get_toggle_excl_bits(addr_ranges: List[List[int]],
     toggle_bits = 0
     for addr in addr_ranges:
         # The size of the address range should be power of 2
-        assert is_pow2(addr[1] - addr[0] + 1)
+        if not is_pow2(addr[1] - addr[0] + 1):
+            return []
 
         toggle_bits |= addr[0]
         toggle_bits |= addr[1] - addr[0]

util/tlgen/validate.py

@@ -368,13 +368,6 @@ def validate(obj: Dict[Any, Any]) -> Optional[Xbar]:
                             % (MIN_DEVICE_SPACING, addr_entry[0], addr_entry[1]))
                         raise SystemExit("Base alignment error occurred")
 
-                    if checkBaseSizeOverlap(address_from, size):
-                        log.error(
-                            "Size mask and base address are overlapping. "
-                            " Check the config. Addr(0x%x - 0x%x)"
-                            % (addr_entry[0], addr_entry[1]))
-                        raise SystemExit("Base/size overlapping error occurred")
-
                     if checkAddressOverlap(addr_entry, addr_range):
                         log.error(
                             "Address is overlapping. Check the config. Addr(0x%x - 0x%x). "

util/tlgen/xbar.pkg.sv.tpl

@@ -5,6 +5,8 @@
 // tl_${xbar.name} package generated by `tlgen.py` tool
 
 <%
+  from tlgen.validate import checkBaseSizeOverlap
+
   addr_spaces = set()
   for host in xbar.hosts:
     addr_spaces |= host.addr_spaces
@@ -45,10 +47,16 @@ package tl_${xbar.name}_pkg;
   lname = uname.ljust(name_len)
   ## The size of the space does not depend on the ASID, so use the first one.
   asid = list(device.addr_spaces)[0]
+  start_addr = device.addr_ranges[asid][0][0]
+  size_bytes = (device.addr_ranges[asid][0][1] - device.addr_ranges[asid][0][0]) + 1
 %>\
   ## Mask
   % if len(device.addr_ranges[asid]) == 1 and not device.xbar:
-  localparam logic [31:0] ADDR_MASK_${lname} = 32'h ${"%08x" % (device.addr_ranges[asid][0][1] - device.addr_ranges[asid][0][0])};
+    % if checkBaseSizeOverlap(start_addr, size_bytes):
+  localparam logic [31:0] ADDR_SIZE_${lname} = 32'h ${"%08x" % size_bytes};
+    % else:
+  localparam logic [31:0] ADDR_MASK_${lname} = 32'h ${"%08x" % (size_bytes - 1)};
+    % endif
   % else:
   localparam logic [${len(device.addr_ranges[asid])-1}:0][31:0] ADDR_MASK_${lname} = {
     % for addr in list(reversed(device.addr_ranges[asid])):

util/tlgen/xbar.rtl.sv.tpl

@@ -9,6 +9,7 @@
 <%
   import tlgen.lib as lib
   from tlgen.item import Host, Device, AsyncFifo, Socket1N, SocketM1
+  from tlgen.validate import checkBaseSizeOverlap
 %>\
 % for host in xbar.hosts:
 ${xbar.repr_tree(host, 0)}
@@ -172,15 +173,18 @@ module xbar_${xbar.name} (
   # name_space = "ADDR_SPACE_" + asid_name + "__" + leaf_name;
   name_space = "ADDR_SPACE_" + leaf_name;
   name_mask  = "ADDR_MASK_" + leaf_name;
+  name_size  = "ADDR_SIZE_" + leaf_name;
   prefix = "if (" if loop.first else "end else if ("
+  start_addr = leaf.addr_ranges[asid][0][0]
+  size_bytes = (leaf.addr_ranges[asid][0][1] - leaf.addr_ranges[asid][0][0]) + 1
 %>\
   % if len(leaf.addr_ranges[asid]) == 1:
-      % if lib.is_pow2((leaf.addr_ranges[asid][0][1]-leaf.addr_ranges[asid][0][0])+1):
+      % if checkBaseSizeOverlap(start_addr, size_bytes) or not lib.is_pow2(size_bytes):
+    ${prefix}((${addr_sig} < (${name_space} + ${name_size})) &&
+       (${addr_sig} >= ${name_space}))) begin
+      % else:
     ${prefix}(${addr_sig} &
     ${" " * len(prefix)} ~(${name_mask})) == ${name_space}) begin
-      % else:
-    ${prefix}((${addr_sig} <= (${name_mask} + ${name_space})) &&
-       (${addr_sig} >= ${name_space}))) begin
       % endif
       dev_sel_${block.name} = ${"%d'd%d" % (sel_len, loop.index)};
 ${"end" if loop.last else ""}
@@ -191,11 +195,11 @@ ${"end" if loop.last else ""}
 %>\
     ${prefix}
     % for i in range(num_range):
-      % if lib.is_pow2(leaf.addr_ranges[asid][i][1]-leaf.addr_ranges[asid][i][0]+1):
-      ((${addr_sig} & ~(${name_mask}[${i}])) == ${name_space}[${i}])${" ||" if not loop.last else ""}
-      % else:
-      ((${addr_sig} <= (${name_mask}[${i}] + ${name_space}[${i}])) &&
+      % if checkBaseSizeOverlap(start_addr, size_bytes) or not lib.is_pow2(size_bytes):
+      ((${addr_sig} < (${name_space}[${i}] + ${name_size}[${i}])) &&
        (${addr_sig} >= ${name_space}[${i}]))${" ||" if not loop.last else ""}
+      % else:
+      ((${addr_sig} & ~(${name_mask}[${i}])) == ${name_space}[${i}])${" ||" if not loop.last else ""}
       % endif
     % endfor
     ) begin

util/topgen/lib.py

@@ -749,16 +749,13 @@ def get_base_and_size(name_to_block: IpBlocksT, inst: ConfigT,
 
                 bytes_used = memory_size
 
-    # Round up to next power of 2.
-    size_byte = 1 << (bytes_used - 1).bit_length()
-
     for (asid, base_addr) in base_addrs.items():
         if isinstance(base_addr, str):
             base_addrs[asid] = int(base_addr, 0)
         else:
             assert isinstance(base_addrs[asid], int)
 
-    return (base_addrs, size_byte)
+    return (base_addrs, bytes_used)
 
 
 def get_io_enum_literal(sig: Dict, prefix: str) -> str: