Merge branch 'tc-l2' into dev

Author: maksyuki

rtl/Makefile

@@ -250,9 +250,13 @@ socPrevBuild: diffAllBuild socTopModify
 socBuild: socPrevBuild
 	$(MAKE) VM_PARALLEL_BUILDS=1 OPT_FAST="-O3" -C $(SOC_COMPILE_HOME) -f V$(SOC_VSRC_TOP).mk -j2
 
-socSimRun:
-	$(SOC_VSRC_HOME)/emu -i $(YSYXSOC_HOME)/program/bin/flash/hello-flash.bin --dump-wave
-
+socRun:
+# $(SOC_VSRC_HOME)/emu -i $(YSYXSOC_HOME)/program/bin/flash/hello-flash.bin
+# $(SOC_VSRC_HOME)/emu -i $(YSYXSOC_HOME)/program/bin/flash/memtest-flash.bin
+# $(SOC_VSRC_HOME)/emu -i $(YSYXSOC_HOME)/program/bin/flash/rtthread-flash.bin
+# $(SOC_VSRC_HOME)/emu -i $(YSYXSOC_HOME)/program/bin/loader/hello-loader.bin
+# $(SOC_VSRC_HOME)/emu -i $(YSYXSOC_HOME)/program/bin/loader/memtest-loader.bin
+# $(SOC_VSRC_HOME)/emu -i $(YSYXSOC_HOME)/program/bin/loader/rtthread-loader.bin
 ###### clean target ######
 cleanBuild:
 	rm -rf $(BUILD_DIR)

rtl/tc_l2/src/main/scala/common/InstConfig.scala

@@ -24,9 +24,9 @@ trait InstConfig {
   // | true  | false |
   // | false | true  |
   // |===============|
-  val DiffEna = true
-  val SoCEna  = false
+  // val DiffEna = true
+  // val SoCEna  = false
   //======================
-  // val DiffEna = false
-  // val SoCEna  = true
+  val DiffEna = false
+  val SoCEna  = true
 }