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AVX512BMM instructions #170

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36 changes: 36 additions & 0 deletions travis/test/avx512bmm.asm
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;Testname=avx512bmm; Arguments=-fbin -oavx512bmm.bin -O0 -DSRC; Files=stdout stderr avx512bmm.bin

%macro testcase 2
%ifdef BIN
db %1
%endif
%ifdef SRC
%2
%endif
%endmacro


bits 64

testcase { 0x62, 0xf6, 0x6c, 0x28, 0x80, 0xd9 }, { VBMACOR16X16X16 ymm3, ymm2, ymm1 }
testcase { 0x62, 0xf6, 0x6c, 0x48, 0x80, 0xd9 }, { VBMACOR16X16X16 zmm3, zmm2, zmm1 }
testcase { 0x62, 0xf6, 0x74, 0x28, 0x80, 0x94, 0xf4, 0xc0, 0x1d, 0xfe, 0xff }, { VBMACOR16X16X16 ymm2, ymm1, yword [rsp+rsi*8-0x1e240] }
testcase { 0x62, 0xf6, 0x74, 0x48, 0x80, 0x94, 0xf4, 0xc0, 0x1d, 0xfe, 0xff }, { VBMACOR16X16X16 zmm2, zmm1, zword [rsp+rsi*8-0x1e240] }

testcase { 0x62, 0xf6, 0xec, 0x28, 0x80, 0xd9 }, { VBMACXOR16X16X16 ymm3, ymm2, ymm1 }
testcase { 0x62, 0xf6, 0xec, 0x48, 0x80, 0xd9 }, { VBMACXOR16X16X16 zmm3, zmm2, zmm1 }
testcase { 0x62, 0xf6, 0xf4, 0x28, 0x80, 0x94, 0xf4, 0xc0, 0x1d, 0xfe, 0xff }, { VBMACXOR16X16X16 ymm2, ymm1, yword [rsp+rsi*8-0x1e240] }
testcase { 0x62, 0xf6, 0xf4, 0x48, 0x80, 0x94, 0xf4, 0xc0, 0x1d, 0xfe, 0xff }, { VBMACXOR16X16X16 zmm2, zmm1, zword [rsp+rsi*8-0x1e240] }

testcase { 0x62, 0xf6, 0x7c, 0x08, 0x81, 0xd1 }, { VBITREV xmm2, xmm1 }
testcase { 0x62, 0xf6, 0x7c, 0x28, 0x81, 0xd1 }, { VBITREV ymm2, ymm1 }
testcase { 0x62, 0xf6, 0x7c, 0x48, 0x81, 0xd1 }, { VBITREV zmm2, zmm1 }
testcase { 0x62, 0xf6, 0x7c, 0x89, 0x81, 0xd1 }, { VBITREV xmm2{k1}{z}, xmm1 }
testcase { 0x62, 0xf6, 0x7c, 0xa9, 0x81, 0xd1 }, { VBITREV ymm2{k1}{z}, ymm1 }
testcase { 0x62, 0xf6, 0x7c, 0xc9, 0x81, 0xd1 }, { VBITREV zmm2{k1}{z}, zmm1 }
testcase { 0x62, 0xf6, 0x7c, 0x08, 0x81, 0x94, 0xf4, 0xc0, 0x1d, 0xfe, 0xff }, { VBITREV xmm2, oword [rsp+rsi*8-0x1e240] }
testcase { 0x62, 0xf6, 0x7c, 0x28, 0x81, 0x94, 0xf4, 0xc0, 0x1d, 0xfe, 0xff }, { VBITREV ymm2, yword [rsp+rsi*8-0x1e240] }
testcase { 0x62, 0xf6, 0x7c, 0x48, 0x81, 0x94, 0xf4, 0xc0, 0x1d, 0xfe, 0xff }, { VBITREV zmm2, zword [rsp+rsi*8-0x1e240] }
testcase { 0x62, 0xf6, 0x7c, 0x89, 0x81, 0x94, 0xf4, 0xc0, 0x1d, 0xfe, 0xff }, { VBITREV xmm2{k1}{z}, oword [rsp+rsi*8-0x1e240] }
testcase { 0x62, 0xf6, 0x7c, 0xa9, 0x81, 0x94, 0xf4, 0xc0, 0x1d, 0xfe, 0xff }, { VBITREV ymm2{k1}{z}, yword [rsp+rsi*8-0x1e240] }
testcase { 0x62, 0xf6, 0x7c, 0xc9, 0x81, 0x94, 0xf4, 0xc0, 0x1d, 0xfe, 0xff }, { VBITREV zmm2{k1}{z}, zword [rsp+rsi*8-0x1e240] }
1 change: 1 addition & 0 deletions travis/test/avx512bmm.bin.t
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b�l(��b�lH��b�t(������b�tH������b��(��b��H��b��(������b��H������b�|��b�|(��b�|H��b�|���b�|���b�|Ɂ�b�|������b�|(������b�|H������b�|�������b�|�������b�|Ɂ�����
18 changes: 18 additions & 0 deletions travis/test/avx512bmm.json
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[
{
"description": "Test AVX512BMM instructions (-Ox)",
"id": "avx512bmm",
"format": "bin",
"source": "avx512bmm.asm",
"option": "-Ox -DSRC",
"target": [
{ "output": "avx512bmm.bin" }
]
},
{
"description": "Test AVX512BMM instructions (-O0)",
"ref": "avx512bmm",
"option": "-O0 -DBIN",
"update": false
}
]
1 change: 1 addition & 0 deletions x86/iflags.ph
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Expand Up @@ -146,6 +146,7 @@ if_("AVX512VPOPCNTDQ", "AVX-512 VPOPCNTD/VPOPCNTQ");
if_("AVX5124FMAPS", "AVX-512 4-iteration multiply-add");
if_("AVX5124VNNIW", "AVX-512 4-iteration dot product");
if_("AVX512FP16", "AVX-512 FP16 instructions");
if_("AVX512BMM", "AVX-512 BMM instructions");
if_("F16C", "F16C instructions");
if_("SGX", "Intel Software Guard Extensions (SGX)");
if_("CET", "Intel Control-Flow Enforcement Technology (CET)");
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8 changes: 8 additions & 0 deletions x86/insns.dat
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Expand Up @@ -5971,6 +5971,14 @@ VMOVD xmmrm32,xmmreg [mr:t1s: evex.128.66.0f.w0
VMOVW xmmreg,xmmrm16 [rm:t1s: evex.128.f3.map5.w0 6e /r ] AVX10_2
VMOVW xmmrm16,xmmreg [mr:t1s: evex.128.f3.map5.w0 7e /r ] AVX10_2

;# AVX512BMM
VBMACOR16X16X16 ymmreg,ymmreg,ymmrm256 [rvm:fv: evex.256.np.map6.w0 80 /r ] AVX512BMM
VBMACOR16X16X16 zmmreg,zmmreg,zmmrm512 [rvm:fv: evex.512.np.map6.w0 80 /r ] AVX512BMM
VBMACXOR16X16X16 ymmreg,ymmreg,ymmrm256 [rvm:fv: evex.256.np.map6.w1 80 /r ] AVX512BMM
VBMACXOR16X16X16 zmmreg,zmmreg,zmmrm512 [rvm:fv: evex.512.np.map6.w1 80 /r ] AVX512BMM
VBITREV xmmreg|mask|z,xmmrm128 [rm:fv: evex.128.np.map6.w0 81 /r ] AVX512BMM
VBITREV ymmreg|mask|z,ymmrm256 [rm:fv: evex.256.np.map6.w0 81 /r ] AVX512BMM
VBITREV zmmreg|mask|z,zmmrm512 [rm:fv: evex.512.np.map6.w0 81 /r ] AVX512BMM

;# Systematic names for the hinting nop instructions
; These should be last in the file
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