Add reference to FPGA optimized RegFile for cv32

cores/cv32e40p/user_manual/source/intro.rst

@@ -1,4 +1,4 @@
-Introduction 
+Introduction
 =============
 
 CV32E40P is a 4-stage in-order 32-bit RISC-V
@@ -11,7 +11,7 @@ ISA. :numref:`blockdiagram` shows a block diagram of the core.
 .. figure:: ../images/CV32E40P_Block_Diagram.png
    :name: blockdiagram
    :align: center
-   :alt: 
+   :alt:
 
    Block Diagram of CV32E40P RISC-V Core
 
@@ -122,11 +122,11 @@ be provided.
 FPGA Synthesis
 --------------
 
-FPGA synthesis is supported for CV32E40P when the flip-flop based register
-file is used. Since latches are not well supported on FPGAs, it is
-crucial to select the flip-flop based register file. The user needs to provide
-a technology specific implementation of a clock gating cell as described 
-in :ref:`clock-gating-cell`. 
+FPGA synthesis is supported for CV32E40P.
+The FPGA-optimized register file implementation should be used.
+The flip-flop based register file is also compatible with FPGA synthesis, however it results in a significantly higher utilization.
+Since latches are not well supported on FPGAs, the latch-based register file should not be used.
+The user needs to provide a technology specific implementation of a clock gating cell as described in :ref:`clock-gating-cell`.
 
 Verification
 ------------

cores/cv32e40p/user_manual/source/register_file.rst

@@ -12,17 +12,19 @@ contain any sequential logic.
 The register file has three read ports and two write ports. Register file reads are performed in the ID stage.
 Register file writes are performed in the WB stage.
 
-There are two flavors of register file available.
+There are three flavors of register file available.
 
  * Flip-flop based (:file:`rtl/cv32e40p_register_file_ff.sv`)
  * Latch-based (:file:`rtl/cv32e40p_register_file_latch.sv`)
+ * FPGA-optimized (:file:`rtl/cv32e40p_register_file_fpga.sv')
 
-Both flavors have their own benefits and trade-offs.
-While the latch-based register file is recommended for ASICs, the
-flip-flop based register file is recommended for FPGA synthesis,
-although both are compatible with either synthesis target. Note the
-flip-flop based register file is significantly larger than the
-latch-based register-file for an ASIC implementation.
+All three flavors have their own benefits and trade-offs.
+The latch-based register file is recommended for ASICs, as it results in the smallest footprint for an ASIC implementation.
+The flip-flop based register file is recommended for simulation purposes.
+The FPGA optimized register file is intended to be used for FPGA synthesis.
+While the latch-based register file is recommended for ASICs, the flip-flop based register file is with either synthesis target.
+Note the flip-flop based register file is significantly larger than the latch-based register-file for an ASIC implementation.
+The FPGA-optimized register file should not be used for ASIC implementations, since this implementation would result in flip-flops lacking asynchronous reset capability.
 
 
 Flip-Flop-Based Register File
@@ -50,6 +52,15 @@ In addition, a technology-specific clock gating cell must be provided to keep th
 This cell must be wrapped in a module called ``cv32e40p_clock_gate``.
 For more information regarding the clock gating cell, checkout :ref:`getting-started`.
 
+FPGA-Optimized Register File
+-----------------------------
+The FPGA register file leverages synchronous-write / asynchronous-read RAM design elements, where available on FPGA targets.
+
+For Xilinx FPGAs, synthesis results in an implementation using RAM32M primitives.
+Using this design with a Xilinx Artya7-100 FPGA conserves around 1600 LUTS and 950 flip-flops at the expense of 144 LUTRAMs for the 31-entry register file as compared to the flip-flop based register file.
+This makes it the **first choice for FPGA synthesis**.
+To select the FPGA-optimized register file, make sure to use the source file ``cv32e40p_register_file_fpga.sv``.
+
 FPU Register File
 -----------------