8278994: riscv: RVC support

src/hotspot/cpu/riscv/assembler_riscv.cpp

@@ -83,7 +83,7 @@ void Assembler::zext_w(Register Rd, Register Rs) {
   add_uw(Rd, Rs, zr);
 }
 
-void Assembler::li(Register Rd, int64_t imm) {
+void Assembler::_li(Register Rd, int64_t imm) {
   // int64_t is in range 0x8000 0000 0000 0000 ~ 0x7fff ffff ffff ffff
   int shift = 12;
   int64_t upper = imm, lower = imm;

src/hotspot/cpu/riscv/c1_LIRAssembler_riscv.cpp

@@ -1322,7 +1322,11 @@ void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Op
   }
 }
 
-void LIR_Assembler::align_call(LIR_Code code) {  }
+void LIR_Assembler::align_call(LIR_Code code) {
+  // With RVC a call instruction (which will be patched later) may get 2-byte aligned and could
+  // span multiple cache lines. See CallStaticJavaDirectNode::compute_padding() for more info.
+  __ align(4);
+}
 
 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
   address call = __ trampoline_call(Address(op->addr(), rtype));
@@ -1344,6 +1348,7 @@ void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
 
 void LIR_Assembler::emit_static_call_stub() {
   address call_pc = __ pc();
+  assert((__ offset() % 4) == 0, "call sites must be properly aligned");
   address stub = __ start_a_stub(call_stub_size());
   if (stub == NULL) {
     bailout("static call stub overflow");

src/hotspot/cpu/riscv/gc/shared/barrierSetAssembler_riscv.cpp

@@ -238,6 +238,9 @@ void BarrierSetAssembler::nmethod_entry_barrier(MacroAssembler* masm) {
     return;
   }
 
+  // RISCV's amoswap instructions require that the memory address must be naturally aligned.
+  __ align(4);
+
   Label skip, guard;
   Address thread_disarmed_addr(xthread, in_bytes(bs_nm->thread_disarmed_offset()));
 
@@ -256,6 +259,7 @@ void BarrierSetAssembler::nmethod_entry_barrier(MacroAssembler* masm) {
 
   __ bind(guard);
 
+  assert(__ offset() % 4 == 0, "bad alignment");
   __ emit_int32(0); // nmethod guard value. Skipped over in common case.
 
   __ bind(skip);

src/hotspot/cpu/riscv/globals_riscv.hpp

@@ -91,6 +91,7 @@ define_pd_global(intx, InlineSmallCode,          1000);
   product(bool, AvoidUnalignedAccesses, true,                                    \
           "Avoid generating unaligned memory accesses")                          \
   product(bool, UseRVV, false, EXPERIMENTAL, "Use RVV instructions")             \
-  product(bool, UseRVB, false, EXPERIMENTAL, "Use RVB instructions")
+  product(bool, UseRVB, false, EXPERIMENTAL, "Use RVB instructions")             \
+  product(bool, UseRVC, false, EXPERIMENTAL, "Use RVC instructions")
 
 #endif // CPU_RISCV_GLOBALS_RISCV_HPP

src/hotspot/cpu/riscv/macroAssembler_riscv.cpp

@@ -88,8 +88,9 @@ static void pass_arg3(MacroAssembler* masm, Register arg) {
   }
 }
 
-void MacroAssembler::align(int modulus) {
-  while (offset() % modulus != 0) { nop(); }
+void MacroAssembler::align(int modulus, int extra_offset) {
+  CompressibleRegion cr(this);
+  while ((offset() + extra_offset) % modulus != 0) { nop(); }
 }
 
 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
@@ -801,6 +802,7 @@ void MacroAssembler::la(Register Rd, Label &label) {
 
   INSN(beq, feq, bnez);
   INSN(bne, feq, beqz);
+
 #undef INSN
 
 
@@ -960,6 +962,7 @@ int MacroAssembler::bitset_to_regs(unsigned int bitset, unsigned char* regs) {
 // Return the number of words pushed
 int MacroAssembler::push_reg(unsigned int bitset, Register stack) {
   DEBUG_ONLY(int words_pushed = 0;)
+  CompressibleRegion cr(this);
 
   unsigned char regs[32];
   int count = bitset_to_regs(bitset, regs);
@@ -981,6 +984,7 @@ int MacroAssembler::push_reg(unsigned int bitset, Register stack) {
 
 int MacroAssembler::pop_reg(unsigned int bitset, Register stack) {
   DEBUG_ONLY(int words_popped = 0;)
+  CompressibleRegion cr(this);
 
   unsigned char regs[32];
   int count = bitset_to_regs(bitset, regs);
@@ -1003,6 +1007,7 @@ int MacroAssembler::pop_reg(unsigned int bitset, Register stack) {
 // Push float registers in the bitset, except sp.
 // Return the number of heapwords pushed.
 int MacroAssembler::push_fp(unsigned int bitset, Register stack) {
+  CompressibleRegion cr(this);
   int words_pushed = 0;
   unsigned char regs[32];
   int count = bitset_to_regs(bitset, regs);
@@ -1022,6 +1027,7 @@ int MacroAssembler::push_fp(unsigned int bitset, Register stack) {
 }
 
 int MacroAssembler::pop_fp(unsigned int bitset, Register stack) {
+  CompressibleRegion cr(this);
   int words_popped = 0;
   unsigned char regs[32];
   int count = bitset_to_regs(bitset, regs);
@@ -1042,6 +1048,7 @@ int MacroAssembler::pop_fp(unsigned int bitset, Register stack) {
 
 #ifdef COMPILER2
 int MacroAssembler::push_vp(unsigned int bitset, Register stack) {
+  CompressibleRegion cr(this);
   int vector_size_in_bytes = Matcher::scalable_vector_reg_size(T_BYTE);
 
   // Scan bitset to accumulate register pairs
@@ -1063,6 +1070,7 @@ int MacroAssembler::push_vp(unsigned int bitset, Register stack) {
 }
 
 int MacroAssembler::pop_vp(unsigned int bitset, Register stack) {
+  CompressibleRegion cr(this);
   int vector_size_in_bytes = Matcher::scalable_vector_reg_size(T_BYTE);
 
   // Scan bitset to accumulate register pairs
@@ -1085,6 +1093,7 @@ int MacroAssembler::pop_vp(unsigned int bitset, Register stack) {
 #endif // COMPILER2
 
 void MacroAssembler::push_call_clobbered_registers_except(RegSet exclude) {
+  CompressibleRegion cr(this);
   // Push integer registers x7, x10-x17, x28-x31.
   push_reg(RegSet::of(x7) + RegSet::range(x10, x17) + RegSet::range(x28, x31) - exclude, sp);
 
@@ -1099,6 +1108,7 @@ void MacroAssembler::push_call_clobbered_registers_except(RegSet exclude) {
 }
 
 void MacroAssembler::pop_call_clobbered_registers_except(RegSet exclude) {
+  CompressibleRegion cr(this);
   int offset = 0;
   for (int i = 0; i < 32; i++) {
     if (i <= f7->encoding() || i >= f28->encoding() || (i >= f10->encoding() && i <= f17->encoding())) {
@@ -1112,15 +1122,18 @@ void MacroAssembler::pop_call_clobbered_registers_except(RegSet exclude) {
 
 // Push all the integer registers, except zr(x0) & sp(x2) & gp(x3) & tp(x4).
 void MacroAssembler::pusha() {
+  CompressibleRegion cr(this);
   push_reg(0xffffffe2, sp);
 }
 
 // Pop all the integer registers, except zr(x0) & sp(x2) & gp(x3) & tp(x4).
 void MacroAssembler::popa() {
+  CompressibleRegion cr(this);
   pop_reg(0xffffffe2, sp);
 }
 
 void MacroAssembler::push_CPU_state(bool save_vectors, int vector_size_in_bytes) {
+  CompressibleRegion cr(this);
   // integer registers, except zr(x0) & ra(x1) & sp(x2) & gp(x3) & tp(x4)
   push_reg(0xffffffe0, sp);
 
@@ -1142,6 +1155,7 @@ void MacroAssembler::push_CPU_state(bool save_vectors, int vector_size_in_bytes)
 }
 
 void MacroAssembler::pop_CPU_state(bool restore_vectors, int vector_size_in_bytes) {
+  CompressibleRegion cr(this);
   // vector registers
   if (restore_vectors) {
     vsetvli(t0, x0, Assembler::e64, Assembler::m8);
@@ -1308,7 +1322,10 @@ int MacroAssembler::pd_patch_instruction_size(address branch, address target) {
     int64_t imm = (intptr_t)target;
     return patch_imm_in_li32(branch, (int32_t)imm);
   } else {
-    tty->print_cr("pd_patch_instruction_size: instruction 0x%x could not be patched!\n", *(unsigned*)branch);
+#ifdef ASSERT
+    tty->print_cr("pd_patch_instruction_size: instruction 0x%x at " INTPTR_FORMAT " could not be patched!\n", *(unsigned*)branch, p2i(branch));
+    Disassembler::decode(branch - 10, branch + 10);
+#endif
     ShouldNotReachHere();
   }
   return -1;
@@ -2917,7 +2934,8 @@ address MacroAssembler::emit_trampoline_stub(int insts_call_instruction_offset,
 
   // make sure 4 byte aligned here, so that the destination address would be
   // 8 byte aligned after 3 intructions
-  while (offset() % wordSize == 0) { nop(); }
+  // when we reach here we may get a 2-byte alignment so need to align it
+  align(wordSize, NativeCallTrampolineStub::data_offset);
 
   relocate(trampoline_stub_Relocation::spec(code()->insts()->start() +
                                             insts_call_instruction_offset));
@@ -2932,6 +2950,7 @@ address MacroAssembler::emit_trampoline_stub(int insts_call_instruction_offset,
   bind(target);
   assert(offset() - stub_start_offset == NativeCallTrampolineStub::data_offset,
          "should be");
+  assert(offset() % wordSize == 0, "address loaded by ld must be 8-byte aligned under riscv64");
   emit_int64((intptr_t)dest);
 
   const address stub_start_addr = addr_at(stub_start_offset);

src/hotspot/cpu/riscv/macroAssembler_riscv.hpp

@@ -49,7 +49,7 @@ class MacroAssembler: public Assembler {
   void safepoint_ifence();
 
   // Alignment
-  void align(int modulus);
+  void align(int modulus, int extra_offset = 0);
 
   // Stack frame creation/removal
   void enter() {
@@ -445,11 +445,11 @@ class MacroAssembler: public Assembler {
   void fsflagsi(unsigned imm);
 
   void beqz(Register Rs, const address &dest);
+  void bnez(Register Rs, const address &dest);
   void blez(Register Rs, const address &dest);
   void bgez(Register Rs, const address &dest);
   void bltz(Register Rs, const address &dest);
   void bgtz(Register Rs, const address &dest);
-  void bnez(Register Rs, const address &dest);
   void la(Register Rd, Label &label);
   void la(Register Rd, const address &dest);
   void la(Register Rd, const Address &adr);

src/hotspot/cpu/riscv/nativeInst_riscv.hpp

@@ -53,7 +53,8 @@ class NativeInstruction {
   friend bool is_NativeCallTrampolineStub_at(address);
  public:
   enum {
-    instruction_size = 4
+    instruction_size = 4,
+    compressed_instruction_size = 2,
   };
 
   juint encoding() const {
@@ -422,10 +423,10 @@ inline NativeMovRegMem* nativeMovRegMem_at (address addr) {
 class NativeJump: public NativeInstruction {
  public:
   enum RISCV64_specific_constants {
-    instruction_size            =    4,
+    instruction_size            =    NativeInstruction::instruction_size,
     instruction_offset          =    0,
     data_offset                 =    0,
-    next_instruction_offset     =    4
+    next_instruction_offset     =    NativeInstruction::instruction_size
   };
 
   address instruction_address() const       { return addr_at(instruction_offset); }

src/hotspot/cpu/riscv/register_riscv.hpp

@@ -58,7 +58,11 @@ class RegisterImpl: public AbstractRegisterImpl {
   enum {
     number_of_registers      = 32,
     number_of_byte_registers = 32,
-    max_slots_per_register   = 2
+    max_slots_per_register   = 2,
+
+    // integer registers in the range of [x8~x15] correspond to RVC. Please see Table 16.2 in spec.
+    compressed_register_base = 8,
+    compressed_register_top  = 15,
   };
 
   // derived registers, offsets, and addresses
@@ -71,10 +75,13 @@ class RegisterImpl: public AbstractRegisterImpl {
 
   // accessors
   int   encoding() const                         { assert(is_valid(), "invalid register"); return (intptr_t)this; }
+  int   compressed_encoding() const              { assert(is_compressed_valid(), "invalid compressed register"); return ((intptr_t)this - compressed_register_base); }
   bool  is_valid() const                         { return 0 <= (intptr_t)this && (intptr_t)this < number_of_registers; }
+  bool  is_compressed_valid() const              { return compressed_register_base <= (intptr_t)this && (intptr_t)this <= compressed_register_top; }
   bool  has_byte_register() const                { return 0 <= (intptr_t)this && (intptr_t)this < number_of_byte_registers; }
   const char* name() const;
   int   encoding_nocheck() const                 { return (intptr_t)this; }
+  int   compressed_encoding_nocheck() const      { return ((intptr_t)this - compressed_register_base); }
 
   // Return the bit which represents this register.  This is intended
   // to be ORed into a bitmask: for usage see class RegSet below.
@@ -131,7 +138,11 @@ class FloatRegisterImpl: public AbstractRegisterImpl {
  public:
   enum {
     number_of_registers     = 32,
-    max_slots_per_register  = 2
+    max_slots_per_register  = 2,
+
+    // float registers in the range of [f8~f15] correspond to RVC. Please see Table 16.2 in spec.
+    compressed_register_base = 8,
+    compressed_register_top  = 15,
   };
 
   // construction
@@ -144,8 +155,11 @@ class FloatRegisterImpl: public AbstractRegisterImpl {
 
   // accessors
   int   encoding() const                          { assert(is_valid(), "invalid register"); return (intptr_t)this; }
+  int   compressed_encoding() const               { assert(is_compressed_valid(), "invalid compressed register"); return ((intptr_t)this - compressed_register_base); }
   int   encoding_nocheck() const                         { return (intptr_t)this; }
+  int   compressed_encoding_nocheck() const       { return ((intptr_t)this - compressed_register_base); }
   bool  is_valid() const                          { return 0 <= (intptr_t)this && (intptr_t)this < number_of_registers; }
+  bool  is_compressed_valid() const               { return compressed_register_base <= (intptr_t)this && (intptr_t)this <= compressed_register_top; }
   const char* name() const;
 
 };