[GPU] enable simd16 version for convolution_gpu_mmad_b_fs_yx_fsv32

src/plugins/intel_gpu/include/intel_gpu/runtime/format.hpp

@@ -189,6 +189,8 @@ struct format {
         os_is_zyx_isa8_osv16_isv4,                    ///< format for weights for fully connected MMAD
         os_is_yx_osa4_isa8_osv8_isv4_swizzled_by_4,   ///< format for weights for MMAD fsv32 convolution
         os_is_zyx_osa4_isa8_osv8_isv4_swizzled_by_4,  ///< format for weights for MMAD fsv32 convolution
+        os_is_yx_osa2_isa8_osv16_isv4_swizzled_by_2,   ///< format for weights for MMAD fsv32 convolution
+        os_is_zyx_osa2_isa8_osv16_isv4_swizzled_by_2,   ///< format for weights for MMAD fsv32 convolution
         os_is_zyx_osa4_isa8_osv8_isv4,                ///< format for weights for MMAD fsv32 convolution
         os_is_yx_osa4_isa8_osv8_isv4,                 ///< format for weights for MMAD fsv32 convolution
         os_is_yx_osv16_isv4,                          ///< format for weights for IMAD convolutions

src/plugins/intel_gpu/src/graph/impls/ocl/kernel_selector_helper.cpp

@@ -538,6 +538,10 @@ kernel_selector::weights_layout to_weights_layout(format f, bool is_grouped) {
             return kernel_selector::weights_layout::os_is_yx_osa4_isa8_osv8_isv4_swizzled_by_4;
         case format::os_is_zyx_osa4_isa8_osv8_isv4_swizzled_by_4:
             return kernel_selector::weights_layout::os_is_zyx_osa4_isa8_osv8_isv4_swizzled_by_4;
+        case format::os_is_yx_osa2_isa8_osv16_isv4_swizzled_by_2:
+            return kernel_selector::weights_layout::os_is_yx_osa2_isa8_osv16_isv4_swizzled_by_2;
+        case format::os_is_zyx_osa2_isa8_osv16_isv4_swizzled_by_2:
+            return kernel_selector::weights_layout::os_is_zyx_osa2_isa8_osv16_isv4_swizzled_by_2;
         case format::os_is_yx_osv16_isv4:
             return kernel_selector::weights_layout::os_is_yx_osv16_isv4;
         case format::os_is_yx_osv32_isv4_swizzled_by_2:
@@ -728,6 +732,10 @@ cldnn::format::type from_weights_layout(kernel_selector::weights_layout l) {
             return cldnn::format::os_is_zyx_isa8_osv16_isv4;
         case kernel_selector::weights_layout::os_is_yx_osa4_isa8_osv8_isv4_swizzled_by_4:
             return cldnn::format::os_is_yx_osa4_isa8_osv8_isv4_swizzled_by_4;
+        case kernel_selector::weights_layout::os_is_yx_osa2_isa8_osv16_isv4_swizzled_by_2:
+            return cldnn::format::os_is_yx_osa2_isa8_osv16_isv4_swizzled_by_2;
+        case kernel_selector::weights_layout::os_is_zyx_osa2_isa8_osv16_isv4_swizzled_by_2:
+            return cldnn::format::os_is_zyx_osa2_isa8_osv16_isv4_swizzled_by_2;
         case kernel_selector::weights_layout::os_is_zyx_osa4_isa8_osv8_isv4_swizzled_by_4:
             return cldnn::format::os_is_zyx_osa4_isa8_osv8_isv4_swizzled_by_4;
         case kernel_selector::weights_layout::os_is_yx_osv32_isv4_swizzled_by_2:

src/plugins/intel_gpu/src/kernel_selector/cl_kernels/include/batch_headers/fetch_weights.cl

@@ -794,6 +794,65 @@ inline uint get_os_is_yx_osa4_isa8_osv8_isv4_swizzled_by_4_index(uint o, uint i,
     return idx;
 }
 
+inline uint get_os_is_yx_osa2_isa8_osv16_isv4_swizzled_by_2_index(
+    uint o, uint i, uint y, uint x,
+    uint size_x, uint size_y,
+    uint size_ifm, uint size_ofm,
+    uint offset)
+{
+    const uint o_swizzled = (o % 2) * 16 + ((o % 32) / 2) + (o / 32) * 32;
+    const uint isv_idx = i % 4;
+    const uint isa_idx = (i / 4) % 8;
+    const uint is_idx  = i / 32;
+    const uint osv_idx = o_swizzled % 16;
+    const uint osa_idx = (o_swizzled / 16) % 2;
+    const uint os_idx  = o / 32;
+
+    const uint f_32_aligned = (size_ifm + 31) / 32;
+
+    size_t idx = offset +
+                 isv_idx +
+                 osv_idx * 4 +
+                 isa_idx * 16 * 4 +
+                 osa_idx * 16 * 32 +
+                 x * 32 * 32 +
+                 y * size_x * 32 * 32 +
+                 is_idx * 32 * 32 * size_x * size_y +
+                 os_idx * 32 * 32 * f_32_aligned * size_x * size_y;
+
+    return idx;
+}
+
+inline uint get_os_is_zyx_osa2_isa8_osv16_isv4_swizzled_by_2_index(
+    uint o, uint i, uint z, uint y, uint x,
+    uint size_x, uint size_y, uint size_z,
+    uint size_ifm, uint size_ofm,
+    uint offset)
+{
+    const uint o_swizzled = (o % 2) * 16 + ((o % 32) / 2) + (o / 32) * 32;
+    const uint isv_idx = i % 4;
+    const uint isa_idx = (i / 4) % 8;
+    const uint is_idx  = i / 32;
+    const uint osv_idx = o_swizzled % 16;
+    const uint osa_idx = (o_swizzled / 16) % 2;
+    const uint os_idx  = o / 32;
+
+    const uint f_32_aligned = (size_ifm + 31) / 32;
+
+    size_t idx = offset +
+                 isv_idx +
+                 osv_idx * 4 +
+                 isa_idx * 16 * 4 +
+                 osa_idx * 16 * 32 +
+                 x * 32 * 32 +
+                 y * size_x * 32 * 32 +
+                 z * size_x * size_y * 32 * 32 +
+                 is_idx * 32 * 32 * size_x * size_y * size_z +
+                 os_idx * 32 * 32 * f_32_aligned * size_x * size_y * size_z;
+
+    return idx;
+}
+
 inline uint get_os_is_zyx_osa4_isa8_osv8_isv4_swizzled_by_4_index(uint o, uint i, uint z, uint y, uint x,
                                                                         uint size_x, uint size_y, uint size_z,
                                                                         uint size_ifm, uint size_ofm, uint offset)
@@ -985,6 +1044,25 @@ inline uint get_g_is_os_yx_isa4_osa8_isv8_osv4(uint g, uint o, uint i, uint z, u
         CAT(prefix, _OFM_NUM),                                                              \
         CAT(prefix, _OFFSET))
 
+#define GET_FILTER_OS_IS_YX_OSA2_ISA8_OSV16_ISV4_SWIZZLED_BY_2_INDEX(prefix, o, i, y, x) \
+    get_os_is_yx_osa2_isa8_osv16_isv4_swizzled_by_2_index(                               \
+        o, i, y, x,                                                                     \
+        CAT(prefix, _SIZE_X),                                                           \
+        CAT(prefix, _SIZE_Y),                                                           \
+        CAT(prefix, _IFM_NUM),                                                          \
+        CAT(prefix, _OFM_NUM),                                                          \
+        CAT(prefix, _OFFSET))
+
+#define GET_FILTER_OS_IS_ZYX_OSA2_ISA8_OSV16_ISV4_SWIZZLED_BY_2_INDEX(prefix, o, i, z, y, x) \
+    get_os_is_zyx_osa2_isa8_osv16_isv4_swizzled_by_2_index(                               \
+        o, i, z, y, x,                                                                     \
+        CAT(prefix, _SIZE_X),                                                           \
+        CAT(prefix, _SIZE_Y),                                                           \
+        CAT(prefix, _SIZE_Z),                                                           \
+        CAT(prefix, _IFM_NUM),                                                          \
+        CAT(prefix, _OFM_NUM),                                                          \
+        CAT(prefix, _OFFSET))
+
 inline uint get_is_o32_yx_isv32_swizzled_by_4_index(uint o, uint i, uint y, uint x, uint i_size, uint o_size, uint x_size, uint y_size)
 {
     const uint o_aligned_to_32 = ((o_size + 31) / 32) * 32;

src/plugins/intel_gpu/src/kernel_selector/cl_kernels/reorder_weights.cl

@@ -431,6 +431,10 @@ inline uint FUNC(get_output_index)(uint g, uint o, uint i, uint z, uint y, uint
     return GET_FILTER_OS_IS_YX_OSA4_ISA8_OSV8_ISV4_SWIZZLED_BY_4_INDEX(OUTPUT, o, i, y, x);
 #elif defined OUTPUT_LAYOUT_OS_IS_ZYX_OSA4_ISA8_OSV8_ISV4_SWIZZLED_BY_4
     return GET_FILTER_OS_IS_ZYX_OSA4_ISA8_OSV8_ISV4_SWIZZLED_BY_4_INDEX(OUTPUT, o, i, z, y, x);
+#elif defined OUTPUT_LAYOUT_OS_IS_YX_OSA2_ISA8_OSV16_ISV4_SWIZZLED_BY_2
+    return GET_FILTER_OS_IS_YX_OSA2_ISA8_OSV16_ISV4_SWIZZLED_BY_2_INDEX(OUTPUT, o, i, y, x);
+#elif defined OUTPUT_LAYOUT_OS_IS_ZYX_OSA2_ISA8_OSV16_ISV4_SWIZZLED_BY_2
+    return GET_FILTER_OS_IS_ZYX_OSA2_ISA8_OSV16_ISV4_SWIZZLED_BY_2_INDEX(OUTPUT, o, i, z, y, x);
 #elif defined OUTPUT_LAYOUT_OS_IS_YX_ISV16_OSV16
     return GET_FILTER_OS_IS_YX_ISV_OSV_INDEX(OUTPUT, o, i, y, x, 16, 16);
 #elif defined OUTPUT_LAYOUT_OS_IS_ZYX_ISV16_OSV16

src/plugins/intel_gpu/src/kernel_selector/kernel_selector_common.cpp

@@ -347,6 +347,8 @@ std::string toString(WeightsLayout layout) {
         case WeightsLayout::os_is_zyx_isa8_osv16_isv4:                   return "OS_IS_ZYX_ISA8_OSV16_ISV4";
         case WeightsLayout::os_is_yx_osa4_isa8_osv8_isv4_swizzled_by_4:  return "OS_IS_YX_OSA4_ISA8_OSV8_ISV4_SWIZZLED_BY_4";
         case WeightsLayout::os_is_zyx_osa4_isa8_osv8_isv4_swizzled_by_4: return "OS_IS_ZYX_OSA4_ISA8_OSV8_ISV4_SWIZZLED_BY_4";
+        case WeightsLayout::os_is_yx_osa2_isa8_osv16_isv4_swizzled_by_2: return "OS_IS_YX_OSA2_ISA8_OSV16_ISV4_SWIZZLED_BY_2";
+        case WeightsLayout::os_is_zyx_osa2_isa8_osv16_isv4_swizzled_by_2: return "OS_IS_ZYX_OSA2_ISA8_OSV16_ISV4_SWIZZLED_BY_2";
         case WeightsLayout::os_is_yx_osv16_isv4:                         return "OS_IS_YX_OSV16_ISV4";
         case WeightsLayout::os_is_yx_osv32_isv4_swizzled_by_2:           return "OS_IS_YX_OSV32_ISV4_SWIZZLED_BY_2";
         case WeightsLayout::os_is_yx_osv32_isv4:                         return "OS_IS_YX_OSV32_ISV4";

src/plugins/intel_gpu/src/kernel_selector/kernels/convolution/convolution_kernel_base.cpp

@@ -410,8 +410,8 @@ Datatype ConvolutionKernelBase::GetPackedInputType(const convolution_params& par
     return GetPackedType(params.inputs[0].GetDType());
 }
 
-Datatype ConvolutionKernelBase::GetPackedOutputType(const convolution_params& params) const {
-    return GetPackedType(params.outputs[0].GetDType());
+Datatype ConvolutionKernelBase::GetPackedOutputType(const convolution_params& params, size_t pack_size) const {
+    return GetPackedType(params.outputs[0].GetDType(), pack_size);
 }
 
 Datatype ConvolutionKernelBase::GetActivationType(const convolution_params& params) const {

src/plugins/intel_gpu/src/kernel_selector/kernels/convolution/convolution_kernel_base.h

@@ -77,7 +77,7 @@ class ConvolutionKernelBase : public WeightBiasKernelBase {
 
     Datatype GetPackedType(Datatype dt, size_t pack_size = 4) const;
     Datatype GetPackedInputType(const convolution_params& params) const;
-    Datatype GetPackedOutputType(const convolution_params& params) const;
+    Datatype GetPackedOutputType(const convolution_params& params, size_t pack_size = 4) const;
     Datatype GetActivationType(const convolution_params& params) const;
     Datatype GetAccumulatorType(const convolution_params& params) const;
     void GetUpdateDispatchDataFunc(KernelData& kd) const override;

src/plugins/intel_gpu/src/kernel_selector/kernels/convolution/convolution_kernel_mmad_b_fs_yx_fsv32.cpp

@@ -63,7 +63,7 @@ bool ConvolutionKernel_mmad_b_fs_yx_fsv32::Validate(const Params& p) const {
         DO_NOT_USE_THIS_KERNEL(p.layerID);
     }
 
-    if (!IsSIMDSizeSupported(params.engineInfo, 8))
+    if (!IsSIMDSizeSupported(params.engineInfo, 8) && !IsSIMDSizeSupported(params.engineInfo, 16))
         DO_NOT_USE_THIS_KERNEL(p.layerID);
 
     if (params.groups > 1)
@@ -109,12 +109,18 @@ ConvolutionKernelBase::DispatchData ConvolutionKernel_mmad_b_fs_yx_fsv32::SetDef
             break;
         ow_group--;
     }
-
-    dispatchData.gws[0] = Align(cp.outputs[0].Feature().v, 32) / 4;
+    if (IsSIMDSizeSupported(cp.engineInfo, 8)) {
+        dispatchData.gws[0] = Align(cp.outputs[0].Feature().v, 32) / 4;
+    } else {
+        dispatchData.gws[0] = Align(cp.outputs[0].Feature().v, 32) / 2;
+    }
     dispatchData.gws[1] = Align(CeilDiv(cp.outputs[0].X().v, dispatchData.cldnnStyle.blockWidth), ow_group) * cp.outputs[0].Y().v * cp.outputs[0].Z().v;
     dispatchData.gws[2] = cp.outputs[0].Batch().v;
-
-    dispatchData.lws[0] = 8;
+    if (IsSIMDSizeSupported(cp.engineInfo, 8)) {
+        dispatchData.lws[0] = 8;
+    } else {
+        dispatchData.lws[0] = 16;
+    }
     dispatchData.lws[1] = ow_group;
     dispatchData.lws[2] = 1;
 
@@ -144,7 +150,11 @@ JitConstants ConvolutionKernel_mmad_b_fs_yx_fsv32::GetJitConstants(const convolu
     jit.AddConstant(MakeJitConstant("INPUT_LINE_SIZE", input_line_size));
 
     jit.Merge(MakeTypeJitConstants(GetPackedInputType(params), "PACKED_IN"));
-    jit.Merge(MakeTypeJitConstants(GetPackedOutputType(params), "PACKED_OUT"));
+    if (IsSIMDSizeSupported(params.engineInfo, 8)) {
+        jit.Merge(MakeTypeJitConstants(GetPackedOutputType(params), "PACKED_OUT"));
+    } else {
+        jit.Merge(MakeTypeJitConstants(GetPackedOutputType(params, 2), "PACKED_OUT"));
+    }
     if (params.weights.GetDType() == WeightsType::INT8) {
         jit.AddConstant(MakeJitConstant("FILTER_TYPE_CHAR", 1));
     } else if (params.weights.GetDType() == WeightsType::UINT8) {
@@ -159,22 +169,26 @@ JitConstants ConvolutionKernel_mmad_b_fs_yx_fsv32::GetJitConstants(const convolu
         std::vector<std::string> idx_order2;
         std::vector<std::string> idx_order3;
         if (DataTensor::ChannelsCount(params.outputs[0].GetLayout()) == 4) {
-            idx_order0 = {"b", "(fg*32 + 4*lid+0)", "y", "(x+i)"};
-            idx_order1 = {"b", "(fg*32 + 4*lid+1)", "y", "(x+i)"};
-            idx_order2 = {"b", "(fg*32 + 4*lid+2)", "y", "(x+i)"};
-            idx_order3 = {"b", "(fg*32 + 4*lid+3)", "y", "(x+i)"};
+            idx_order0 = {"b", "(fg*32 + OF_TO_DO*lid+0)", "y", "(x+i)"};
+            idx_order1 = {"b", "(fg*32 + OF_TO_DO*lid+1)", "y", "(x+i)"};
+            idx_order2 = {"b", "(fg*32 + OF_TO_DO*lid+2)", "y", "(x+i)"};
+            idx_order3 = {"b", "(fg*32 + OF_TO_DO*lid+3)", "y", "(x+i)"};
         } else if (DataTensor::ChannelsCount(params.outputs[0].GetLayout()) == 5) {
-            idx_order0 = {"b", "(fg*32 + 4*lid+0)", "z", "y", "(x+i)"};
-            idx_order1 = {"b", "(fg*32 + 4*lid+1)", "z", "y", "(x+i)"};
-            idx_order2 = {"b", "(fg*32 + 4*lid+2)", "z", "y", "(x+i)"};
-            idx_order3 = {"b", "(fg*32 + 4*lid+3)", "z", "y", "(x+i)"};
+            idx_order0 = {"b", "(fg*32 + OF_TO_DO*lid+0)", "z", "y", "(x+i)"};
+            idx_order1 = {"b", "(fg*32 + OF_TO_DO*lid+1)", "z", "y", "(x+i)"};
+            idx_order2 = {"b", "(fg*32 + OF_TO_DO*lid+2)", "z", "y", "(x+i)"};
+            idx_order3 = {"b", "(fg*32 + OF_TO_DO*lid+3)", "z", "y", "(x+i)"};
         }
 
         FusedOpsConfiguration conf0 = {"_0", idx_order0, "res0", input_dt, 1 };
         FusedOpsConfiguration conf1 = {"_1", idx_order1, "res1", input_dt, 1 };
         FusedOpsConfiguration conf2 = {"_2", idx_order2, "res2", input_dt, 1 };
         FusedOpsConfiguration conf3 = {"_3", idx_order3, "res3", input_dt, 1 };
-        jit.Merge(MakeFusedOpsJitConstants(params, {conf0, conf1, conf2, conf3}));
+        if (IsSIMDSizeSupported(params.engineInfo, 8)) {
+            jit.Merge(MakeFusedOpsJitConstants(params, {conf0, conf1, conf2, conf3}));
+        } else {
+            jit.Merge(MakeFusedOpsJitConstants(params, {conf0, conf1}));
+        }
     }
 
     return jit;

src/plugins/intel_gpu/src/kernel_selector/kernels/convolution/convolution_kernel_mmad_b_fs_yx_fsv32.h

@@ -29,10 +29,18 @@ class ConvolutionKernel_mmad_b_fs_yx_fsv32 : public ConvolutionKernelBase {
     bool NeedPaddedInput() const override { return false; }
 
     WeightsLayout GetPreferredWeightsLayout(const convolution_params &p) const override {
-        if (DataTensor::ChannelsCount(p.outputs[0].GetLayout()) <= 4) {
-            return WeightsLayout::os_is_yx_osa4_isa8_osv8_isv4_swizzled_by_4;
+         if (IsSIMDSizeSupported(p.engineInfo, 8)) {
+            if (DataTensor::ChannelsCount(p.outputs[0].GetLayout()) <= 4) {
+                return WeightsLayout::os_is_yx_osa4_isa8_osv8_isv4_swizzled_by_4;
+            } else {
+                return WeightsLayout::os_is_zyx_osa4_isa8_osv8_isv4_swizzled_by_4;
+            }
         } else {
-            return WeightsLayout::os_is_zyx_osa4_isa8_osv8_isv4_swizzled_by_4;
+            if (DataTensor::ChannelsCount(p.outputs[0].GetLayout()) <= 4) {
+                return WeightsLayout::os_is_yx_osa2_isa8_osv16_isv4_swizzled_by_2;
+            } else {
+                return WeightsLayout::os_is_zyx_osa2_isa8_osv16_isv4_swizzled_by_2;
+            }
         }
     }
     std::vector<FusedOpType> GetSupportedFusedOps() const override {

src/plugins/intel_gpu/src/kernel_selector/tensor_type.cpp

@@ -114,6 +114,8 @@ WeightsTensor::WeightsChannelArray WeightsTensor::weightsChannelArray {{
     { WeightsLayout::os_is_zyx_isa8_osv16_isv4,                   {  0,  1,  2,   3,   4, -1 } },
     { WeightsLayout::os_is_yx_osa4_isa8_osv8_isv4_swizzled_by_4,  {  0,  1, -1,   2,   3, -1 } },
     { WeightsLayout::os_is_zyx_osa4_isa8_osv8_isv4_swizzled_by_4, {  0,  1,  2,   3,   4, -1 } },
+    { WeightsLayout::os_is_yx_osa2_isa8_osv16_isv4_swizzled_by_2,  {  0,  1, -1,   2,   3, -1 } },
+    { WeightsLayout::os_is_zyx_osa2_isa8_osv16_isv4_swizzled_by_2, {  0,  1,  2,   3,   4, -1 } },
     { WeightsLayout::os_is_yx_osv8_isv4,                          {  0,  1, -1,   2,   3, -1 } },
     { WeightsLayout::os_is_yx_osv16_isv4,                         {  0,  1, -1,   2,   3, -1 } },
     { WeightsLayout::os_is_yx_osv32_isv4_swizzled_by_2,           {  0,  1, -1,   2,   3, -1 } },
@@ -629,11 +631,13 @@ NDims WeightsTensor::GetSimpleDims(const std::vector<size_t>& d, WeightsLayout l
             newDims[4] = RoundUp(newDims[4], 16);
             break;
         case os_is_yx_osa4_isa8_osv8_isv4_swizzled_by_4:
+        case os_is_yx_osa2_isa8_osv16_isv4_swizzled_by_2:
             assert(newDims.size() == 4);
             newDims[3] = RoundUp(newDims[3], 32);
             newDims[2] = RoundUp(newDims[2], 32);
             break;
         case os_is_zyx_osa4_isa8_osv8_isv4_swizzled_by_4:
+        case os_is_zyx_osa2_isa8_osv16_isv4_swizzled_by_2:
             assert(newDims.size() == 5);
             newDims[4] = RoundUp(newDims[4], 32);
             newDims[3] = RoundUp(newDims[3], 32);

src/plugins/intel_gpu/src/kernel_selector/tensor_type.h

@@ -140,6 +140,8 @@ enum WeightsLayout {
                                                  // 1,5...
     os_is_zyx_osa4_isa8_osv8_isv4_swizzled_by_4,  // for MMAD convolution swizzled from ofm 0..7 to 0,4,8,12,16,20,24,28,
                                                   // 1,5...
+    os_is_yx_osa2_isa8_osv16_isv4_swizzled_by_2,
+    os_is_zyx_osa2_isa8_osv16_isv4_swizzled_by_2,
     os_is_yx_osv16_isv4,                 // swizzled weights for convolution using IMAD
     os_is_yx_osv8_isv4,                      // weights for int8 blocked conv
     os_is_yx_osv32_isv4_swizzled_by_2,   //  weights for bfyx -> b_fs_yx_fsv32 convolution using IMAD with swizzled ofm (0, 2, 4..), (1, 3, 5...)

src/plugins/intel_gpu/src/runtime/format.cpp

@@ -107,6 +107,8 @@ static const std::map<format::type, format_traits> format_traits_map {
         FMT_TRAITS(os_is_zyx_isa8_osv16_isv4,                    1, 1, 3, 0, {0, 1, 2, 3, 4}, "oizyx",  "oixyz", {{1, 8}, {0, 16}, {1, 4}},         {{1, 8}, {0, 16}, {1, 4}}),  // NOLINT
         FMT_TRAITS(os_is_yx_osa4_isa8_osv8_isv4_swizzled_by_4,   1, 1, 2, 0, {0, 1, 2, 3},    "oiyx",   "oixy",  {{0, 32}, {1, 32}},                {{0, 32}, {1, 32}}),  // NOLINT
         FMT_TRAITS(os_is_zyx_osa4_isa8_osv8_isv4_swizzled_by_4,  1, 1, 3, 0, {0, 1, 2, 3, 4}, "oizyx",  "oixyz", {{0, 32}, {1, 32}},                {{0, 32}, {1, 32}}),  // NOLINT
+        FMT_TRAITS(os_is_yx_osa2_isa8_osv16_isv4_swizzled_by_2,   1, 1, 2, 0, {0, 1, 2, 3},    "oiyx",   "oixy",  {{0, 32}, {1, 32}},                {{0, 32}, {1, 32}}),  // NOLINT
+        FMT_TRAITS(os_is_zyx_osa2_isa8_osv16_isv4_swizzled_by_2,   1, 1, 3, 0, {0, 1, 2, 3, 4}, "oizyx",  "oixyz", {{0, 32}, {1, 32}},                {{0, 32}, {1, 32}}),  // NOLINT
         FMT_TRAITS(os_is_yx_osv16_isv4,                          1, 1, 2, 0, {0, 1, 2, 3},    "oiyx",   "oixy",  {{0, 16}, {1, 4}},                 {{0, 16}, {1, 4}}),  // NOLINT
         FMT_TRAITS(os_is_yx_osv8_isv4,                           1, 1, 2, 0, {0, 1, 2, 3},    "oiyx",   "oixy",  {{0, 8}, {1, 4}},                  {{0, 8}, {1, 4}}),  // NOLINT
         FMT_TRAITS(os_is_zyx_osv16_isv16,                        1, 1, 3, 0, {0, 1, 2, 3, 4}, "oizyx",  "oixyz", {{0, 16}, {1, 16}},                {{0, 16}, {1, 16}}),  // NOLINT