Merge pull request #272 from pulp-platform/synth_chan_compare-tbenz

Add synthesizable verification modules that compare two buses and two slave devices.

Author: thommythomaso

Bender.yml

@@ -35,6 +35,7 @@ sources:
   # Level 2
   - src/axi_atop_filter.sv
   - src/axi_burst_splitter.sv
+  - src/axi_bus_compare.sv
   - src/axi_cdc_dst.sv
   - src/axi_cdc_src.sv
   - src/axi_cut.sv
@@ -58,6 +59,7 @@ sources:
   - src/axi_modify_address.sv
   - src/axi_mux.sv
   - src/axi_serializer.sv
+  - src/axi_slave_compare.sv
   - src/axi_throttle.sv
   - src/axi_to_mem.sv
   # Level 3
@@ -97,6 +99,7 @@ sources:
       # Level 1
       - test/tb_axi_addr_test.sv
       - test/tb_axi_atop_filter.sv
+      - test/tb_axi_bus_compare.sv
       - test/tb_axi_cdc.sv
       - test/tb_axi_delayer.sv
       - test/tb_axi_dw_downsizer.sv
@@ -112,6 +115,7 @@ sources:
       - test/tb_axi_modify_address.sv
       - test/tb_axi_serializer.sv
       - test/tb_axi_sim_mem.sv
+      - test/tb_axi_slave_compare.sv
       - test/tb_axi_to_axi_lite.sv
       - test/tb_axi_to_mem_banked.sv
       - test/tb_axi_xbar.sv

CHANGELOG.md

@@ -9,6 +9,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
 
 ### Added
 - Add `axi_channel_compare.sv`: Non-synthesizable module comparing two AXI channels of the same type
+- Add `axi_bus_compare` and `axi_slave_compare`; two synthesizable verification IPs meant to be used
+  to compare two AXI buses on an FPGA.
 
 ### Changed
 - `axi_demux`: Replace FIFO between AW and W channel by a register plus a counter.  This prevents

README.md

@@ -61,6 +61,15 @@ In addition to the documents linked in the following table, we are setting up [d
 | [`axi_xbar`](src/axi_xbar.sv)                        | Fully-connected AXI4+ATOP crossbar with an arbitrary number of slave and master ports.               | [Doc](doc/axi_xbar.md)         |
 | [`axi_xp`](src/axi_xp.sv)                            | AXI Crosspoint (XP) with homomorphous slave and master ports.                                        |                                |
 
+## Synthesizable Verification Modules
+
+The following modules are meant to be used for verification purposes only but are synthesizable to be used in FPGA environments.
+
+| Name                                                 | Description                                                                                             |
+|------------------------------------------------------|---------------------------------------------------------------------------------------------------------|
+| [`axi_bus_compare`](src/axi_bus_compare.sv)          | Compares two buses of the same type (and in the same clock domain), returns events on mismatch.         |
+| [`axi_slave_compare`](src/axi_slave_compare.sv)      | Compares two slave devices of the same type (and in the same clock domain), returns events on mismatch. |
+
 ### Simulation-Only Modules
 
 In addition to the modules above, which are available in synthesis and simulation, the following modules are available only in simulation.  Those modules are widely used in our testbenches, but they are also suitable to build testbenches for AXI modules and systems outside this repository.

axi.core

@@ -17,6 +17,7 @@ filesets:
       # Level 2
       - src/axi_atop_filter.sv
       - src/axi_burst_splitter.sv
+      - src/axi_bus_compare.sv
       - src/axi_cdc_dst.sv
       - src/axi_cdc_src.sv
       - src/axi_cut.sv
@@ -40,6 +41,7 @@ filesets:
       - src/axi_modify_address.sv
       - src/axi_mux.sv
       - src/axi_serializer.sv
+      - src/axi_slave_compare.sv
       - src/axi_throttle.sv
       - src/axi_to_mem.sv
       # Level 3
@@ -73,6 +75,7 @@ filesets:
       - test/axi_synth_bench.sv
       - test/tb_axi_addr_test.sv
       - test/tb_axi_atop_filter.sv
+      - test/tb_axi_bus_compare.sv
       - test/tb_axi_cdc.sv
       - test/tb_axi_delayer.sv
       - test/tb_axi_dw_downsizer.sv
@@ -88,6 +91,7 @@ filesets:
       - test/tb_axi_modify_address.sv
       - test/tb_axi_serializer.sv
       - test/tb_axi_sim_mem.sv
+      - test/tb_axi_slave_compare.sv
       - test/tb_axi_to_axi_lite.sv
       - test/tb_axi_to_mem_banked.sv
       - test/tb_axi_xbar.sv