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scripts(synopsys): Accept arguments for analyze call #227

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scripts(synopsys): Accept arguments for analyze call #227

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b05376d
scripts(synopsys): Accept arguments for `analyze` call
fischeti Oct 31, 2025
63a8803
Make linter happy
fischeti Oct 31, 2025
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15 changes: 15 additions & 0 deletions src/cmd/script.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -93,6 +93,14 @@ pub fn new() -> Command {
.action(ArgAction::Append)
.value_parser(value_parser!(String)),
)
.arg(
Arg::new("synopsys-arg")
.long("synopsys-arg")
.help("Pass an argument to synopsys calls")
.num_args(1..)
.action(ArgAction::Append)
.value_parser(value_parser!(String)),
)
.arg(
Arg::new("only-defines")
.long("only-defines")
Expand Down Expand Up @@ -662,6 +670,13 @@ fn emit_template(
[].to_vec()
};
tera_context.insert("vcom_args", &vcom_args);
let synopsys_args: Vec<String> = if let Some(args) = matches.get_many::<String>("synopsys-arg")
{
args.map(Into::into).collect()
} else {
[].to_vec()
};
tera_context.insert("synopsys_args", &synopsys_args);

tera_context.insert("vlogan_bin", &matches.get_one::<String>("vlogan-bin"));
tera_context.insert("vhdlan_bin", &matches.get_one::<String>("vhdlan-bin"));
Expand Down
8 changes: 7 additions & 1 deletion src/script_fmt/synopsys_tcl.tera
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Expand Up @@ -9,7 +9,9 @@ set search_path $search_path_initial
{% endfor %}
{% if abort_on_error %}if {0 == [{% endif %}{# Catch errors immediately
#}analyze -format {% if group.file_type == 'verilog' %}sv{% elif group.file_type == 'vhdl' %}vhdl{% endif %} \{# Analyze command for SystemVerilog or VHDL #}
{% for define in group.defines %}{# Add group's defines
{% for tmp_arg in synopsys_args %}{{ tmp_arg }} \
{% endfor %}{# Additional command arguments
#}{% for define in group.defines %}{# Add group's defines
#}{% if loop.first %}-define { \
{% endif %}{{ define.0 }}{% if define.1 %}={{ define.1 }}{% endif %}{% if loop.last %} \
} \
Expand All @@ -28,6 +30,8 @@ set search_path $search_path_initial
{% endfor %}
{% if abort_on_error %}if {0 == [{% endif %}{# Catch errors immediately
#}analyze -format sv \{# Analyze command for SystemVerilog #}
{% for tmp_arg in synopsys_args %}{{ tmp_arg }} \
{% endfor %}{# Additional command arguments #}
{% for define in all_defines %}{# Add all defines
}
#}{% if loop.first %}-define { \
Expand All @@ -42,6 +46,8 @@ set search_path $search_path_initial
{% for file in all_vhdl %}{% if loop.first %}{# Loop over all VHDL files
#}{% if abort_on_error %}if {0 == [{% endif %}{# Catch errors immediately
#}analyze -format vhdl \{# Analyze command for VHDL #}
{% for tmp_arg in synopsys_args %}{{ tmp_arg }} \
{% endfor %}{# Additional command arguments #}
[list \
{% endif %}{{ ' ' }}"{{ file | replace(from=root, to='$ROOT') }}" \{# Add all VHDL files #}
{% if loop.last %}]
Expand Down