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Pull requests: riscv-collab/riscv-openocd

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Pull requests list

Breakpoint size auto selection
#1288 opened Sep 8, 2025 by AlexandraKulyatskaya Loading…
target/riscv: hard reset DTM if dmistat is busy
#1287 opened Sep 4, 2025 by lz-bro Loading…
target/riscv: access registers via reg->type
#1269 opened Jun 20, 2025 by en-sc Loading…
target/riscv: warn about truncating register values
#1268 opened Jun 20, 2025 by en-sc Loading…
target/riscv: Fix some timeout check order
#1265 opened Jun 13, 2025 by lz-bro Loading…
target/riscv: extend trigger controls
#1261 opened May 28, 2025 by lz-bro Loading…
target/riscv: fix riscv_mmu behaviour
#1256 opened May 14, 2025 by fk-sc Loading…
Add dcsr cetrig control
#1255 opened May 13, 2025 by lz-bro Loading…
target/riscv: Adjust to upstream coding style
#1254 opened May 6, 2025 by berolinux Loading…
target/riscv: active dm before get nextdm
#1252 opened May 6, 2025 by lz-bro Loading…
target/riscv: Add support for external triggers
#1243 opened Mar 31, 2025 by lz-bro Loading…
target/riscv: Add support for external triggers
#1179 opened Dec 2, 2024 by rbradford Loading…
enable additional platforms in CI
#1121 opened Aug 30, 2024 by aap-sc Loading…
Fix error on exit with uninitialized target
#1015 opened Feb 11, 2024 by tom-van Loading…
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