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Add clint, clic, csrind to S_extensions variable#169

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Add clint, clic, csrind to S_extensions variable#169
dansmathers wants to merge 1 commit intoriscv-software-src:devfrom
dansmathers:patch-1

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@dansmathers dansmathers commented Feb 6, 2024

Description

Provide a detailed description of the changes performed by the PR.

Related Issues

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List the extensions that your PR affects. In case of unratified extensions, please provide a link to the spec draft that was referred to make this PR.

Mandatory Checklist:

  • Make sure you have updated the versions in setup.cfg and riscv_config/__init__.py. Refer to CONTRIBUTING.rst file for further information.
  • Make sure to have created a suitable entry in the CHANGELOG.md.

@dansmathers
Add clint, clic, csrind to S_extensions variable
d55c0ed 
Signed-off-by: Dan Smathers <dan.smathers@seagate.com>
dansmathers added a commit to dansmathers/riscv-arch-test that referenced this pull request Feb 6, 2024
@dansmathers
Add interrupt test cases using clint MSW and MTIMER interrupts
6642c22 
requires 
riscv-software-src/riscv-config#169, 
riscv-software-src/riscof#106

To include these tests in riscof testlist flow, add Smclint to riscof yaml file, e.g.:
spike/spike_isa.yaml:
  ISA: RV32IMCZicsr_Zifencei_Smclint



Signed-off-by: Dan Smathers <dan.smathers@seagate.com>
@dansmathers dansmathers mentioned this pull request Feb 6, 2024
Open
6 tasks
dansmathers added a commit to dansmathers/riscv-arch-test that referenced this pull request Feb 8, 2024
@dansmathers
Draft: Add m-mode CLIC interrupt testcases
0653f78 
This is a draft version of the m-mode (Smclic) CLIC interrupt testcases using clint MSW and MTIMER macros.

Note, pulls are not yet available for spike or sail that support CLIC but these testcases should help enable their development. 

This pull requires:
riscv-software-src/riscv-config#169, 
riscv-software-src/riscof#106
riscv-software-src/riscv-isa-sim#1596

To include m-mode CLIC interrupt tests in riscof testlist flow, add Smclic to riscof yaml file, e.g.:
spike/spike_isa.yaml:
  ISA: RV32IMCZicsr_Zifencei_Smclic


Signed-off-by: Dan Smathers <dan.smathers@seagate.com>
dansmathers added a commit to dansmathers/riscv-arch-test that referenced this pull request Feb 8, 2024
@dansmathers
Draft: Add m-mode CLIC interrupt testcases
11afbf0 
This is a draft version of the m-mode (Smclic) CLIC interrupt testcases using clint MSW and MTIMER macros.

Note, pulls are not yet available for spike or sail that support CLIC but these testcases should help enable their development. 

This pull requires:
riscv-software-src/riscv-config#169, 
riscv-software-src/riscof#106
riscv-software-src/riscv-isa-sim#1596

To include m-mode CLIC interrupt tests in riscof testlist flow, add Smclic to riscof yaml file, e.g.:
spike/spike_isa.yaml:
  ISA: RV32IMCZicsr_Zifencei_Smclic

Signed-off-by: Dan Smathers <dan.smathers@seagate.com>
dansmathers added a commit to dansmathers/riscv-arch-test that referenced this pull request Feb 9, 2024
@dansmathers
Draft: Add s-mode CLIC interrupt testcases
132fe70 
his is a draft version of the s-mode (Ssclic) CLIC interrupt testcases using clint MSW and MTIMER macros.

Note: pulls are not yet available for spike or sail that support CLIC but these testcases should help enable their development. 

This pull requires:
riscv-software-src/riscv-config#169, 
riscv-software-src/riscof#106
riscv-software-src/riscv-isa-sim#1596

To include s-mode CLIC interrupt tests in riscof testlist flow, add Ssclic to riscof yaml file, e.g.:
spike/spike_isa.yaml:
  ISA: RV32IMCZicsr_Zifencei_Ssclic


Signed-off-by: Dan Smathers <dan.smathers@seagate.com>
dansmathers added a commit to dansmathers/riscv-arch-test that referenced this pull request Feb 9, 2024
@dansmathers
Draft: Add s-mode CLIC interrupt testcases
547805c 
This is a draft version of the s-mode (Ssclic) CLIC interrupt testcases using clint MSW and MTIMER macros.

Note: pulls are not yet available for spike or sail that support CLIC but these testcases should help enable their development. 

This pull requires:
riscv-software-src/riscv-config#169, 
riscv-software-src/riscof#106
riscv-software-src/riscv-isa-sim#1596

To include s-mode CLIC interrupt tests in riscof testlist flow, add Ssclic to riscof yaml file, e.g.:
spike/spike_isa.yaml:
  ISA: RV32IMCZicsr_Zifencei_Ssclic


Signed-off-by: Dan Smathers <dan.smathers@seagate.com>
dansmathers added a commit to dansmathers/riscv-arch-test that referenced this pull request Feb 9, 2024
@dansmathers
Draft: Add m/s-mode CLIC interrupt testcases
34d0c72 
This is a draft version of the m-mode (Smclic), s-mode (Ssclic) CLIC interrupt testcases using clint MSW and MTIMER macros.

Note: pulls are not yet available for spike or sail that support CLIC but these testcases should help enable their development. 

This pull requires:
riscv-software-src/riscv-config#169, 
riscv-software-src/riscof#106
riscv-software-src/riscv-isa-sim#1596

To include m-mode CLIC interrupt tests in riscof testlist flow, add Smclic to riscof yaml file, e.g.:
spike/spike_isa.yaml:
  ISA: RV32IMCZicsr_Zifencei_Smclic

To include s-mode CLIC interrupt tests in riscof testlist flow, add Ssclic to riscof yaml file, e.g.:
spike/spike_isa.yaml:
  ISA: RV32IMCZicsr_Zifencei_Ssclic


Signed-off-by: Dan Smathers <dan.smathers@seagate.com>
@dansmathers dansmathers mentioned this pull request Feb 9, 2024
Draft
7 tasks
This was referenced Mar 1, 2024
Open
Closed
@jamesbeyond jamesbeyond changed the base branch from master to dev May 28, 2024 16:24
jamesbeyond pushed a commit to dansmathers/riscv-arch-test that referenced this pull request Jun 6, 2024
@dansmathers @jamesbeyond
Draft: Add m-mode CLIC interrupt testcases
c239aef 
This is a draft version of the m-mode (Smclic) CLIC interrupt testcases using clint MSW and MTIMER macros.

Note, pulls are not yet available for spike or sail that support CLIC but these testcases should help enable their development. 

This pull requires:
riscv-software-src/riscv-config#169, 
riscv-software-src/riscof#106
riscv-software-src/riscv-isa-sim#1596

To include m-mode CLIC interrupt tests in riscof testlist flow, add Smclic to riscof yaml file, e.g.:
spike/spike_isa.yaml:
  ISA: RV32IMCZicsr_Zifencei_Smclic


Signed-off-by: Dan Smathers <dan.smathers@seagate.com>
jamesbeyond pushed a commit to dansmathers/riscv-arch-test that referenced this pull request Jun 6, 2024
@dansmathers @jamesbeyond
Draft: Add m-mode CLIC interrupt testcases
09cb8de 
This is a draft version of the m-mode (Smclic) CLIC interrupt testcases using clint MSW and MTIMER macros.

Note, pulls are not yet available for spike or sail that support CLIC but these testcases should help enable their development. 

This pull requires:
riscv-software-src/riscv-config#169, 
riscv-software-src/riscof#106
riscv-software-src/riscv-isa-sim#1596

To include m-mode CLIC interrupt tests in riscof testlist flow, add Smclic to riscof yaml file, e.g.:
spike/spike_isa.yaml:
  ISA: RV32IMCZicsr_Zifencei_Smclic

Signed-off-by: Dan Smathers <dan.smathers@seagate.com>
jamesbeyond pushed a commit to dansmathers/riscv-arch-test that referenced this pull request Jun 6, 2024
@dansmathers @jamesbeyond
Draft: Add s-mode CLIC interrupt testcases
68e9b39 
his is a draft version of the s-mode (Ssclic) CLIC interrupt testcases using clint MSW and MTIMER macros.

Note: pulls are not yet available for spike or sail that support CLIC but these testcases should help enable their development. 

This pull requires:
riscv-software-src/riscv-config#169, 
riscv-software-src/riscof#106
riscv-software-src/riscv-isa-sim#1596

To include s-mode CLIC interrupt tests in riscof testlist flow, add Ssclic to riscof yaml file, e.g.:
spike/spike_isa.yaml:
  ISA: RV32IMCZicsr_Zifencei_Ssclic


Signed-off-by: Dan Smathers <dan.smathers@seagate.com>
jamesbeyond pushed a commit to dansmathers/riscv-arch-test that referenced this pull request Jun 6, 2024
@dansmathers @jamesbeyond
Draft: Add s-mode CLIC interrupt testcases
35ee9c1 
This is a draft version of the s-mode (Ssclic) CLIC interrupt testcases using clint MSW and MTIMER macros.

Note: pulls are not yet available for spike or sail that support CLIC but these testcases should help enable their development. 

This pull requires:
riscv-software-src/riscv-config#169, 
riscv-software-src/riscof#106
riscv-software-src/riscv-isa-sim#1596

To include s-mode CLIC interrupt tests in riscof testlist flow, add Ssclic to riscof yaml file, e.g.:
spike/spike_isa.yaml:
  ISA: RV32IMCZicsr_Zifencei_Ssclic


Signed-off-by: Dan Smathers <dan.smathers@seagate.com>
jamesbeyond pushed a commit to dansmathers/riscv-arch-test that referenced this pull request Jun 6, 2024
@dansmathers @jamesbeyond
Draft: Add m/s-mode CLIC interrupt testcases
2e3b80b 
This is a draft version of the m-mode (Smclic), s-mode (Ssclic) CLIC interrupt testcases using clint MSW and MTIMER macros.

Note: pulls are not yet available for spike or sail that support CLIC but these testcases should help enable their development. 

This pull requires:
riscv-software-src/riscv-config#169, 
riscv-software-src/riscof#106
riscv-software-src/riscv-isa-sim#1596

To include m-mode CLIC interrupt tests in riscof testlist flow, add Smclic to riscof yaml file, e.g.:
spike/spike_isa.yaml:
  ISA: RV32IMCZicsr_Zifencei_Smclic

To include s-mode CLIC interrupt tests in riscof testlist flow, add Ssclic to riscof yaml file, e.g.:
spike/spike_isa.yaml:
  ISA: RV32IMCZicsr_Zifencei_Ssclic


Signed-off-by: Dan Smathers <dan.smathers@seagate.com>
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