feat: DA^RE power, VE indexed-assign fix, LOOP while-loop rewrite (v1.3.0)#94
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- DA/CD ^ RE: make da_powi/cd_powi pub in polval.rs; add TypeRule entries and RosyPow<&RE> impls for DA and CD in pow.rs - VE indexed assign: wire_inference_edges now resolves VE(i) as RE instead of staying VE when base_type==VE and dimensions==0 - LOOP: replace for-range/step_by with while-loop pattern — fixes float step support and allows iterator mutation inside the body - embedded.rs: add [workspace] to generated Cargo.toml so rosy_output crate doesn't interfere with the parent workspace
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Summary
da_powi/cd_powiinpolval.rsmadepub; newTypeRuleentries andRosyPow<&RE>impls added for bothDAandCDinpow.rswire_inference_edgesinassign/mod.rsnow correctly resolvesV(i) := expras assigning toREwhenVis a plainVE(previously stayedVE, causing false type errors)loop/mod.rsnow generates awhile-loop instead offor I in (start..=end).step_by(...)— fixes float step support and allows iterator variable mutation inside the body[workspace]section to generatedCargo.tomlso therosy_outputcrate doesn't accidentally join the parent workspaceTest plan
DA ^ REintegration test:X := DA(1); R := X ^ 3;produces x₁³ term correctlyV(2) := 20.0; E := V(2)round-trips without type errorLOOP I 1 5sums to 15;LOOP I 0 2 1sums to 3cargo test— 21/21 pass