Pinned Loading

1. ORFS-SMT-RepairTiming ORFS-SMT-RepairTiming Public

   A PyZ3-based closed-loop SMT solver for optimal buffer resizing in OpenROAD-flow-scripts using non-linear formal timing models.

   Python

2. vivaldi vivaldi Public

   A mini FPGA synthesizer built for the Nexys Video Artix-7 FPGA from Digilent.

   SystemVerilog 5

3. manim-digital manim-digital Public

   A Manim library that implements combinational and sequential digital logic components.

   Python 1

4. FPGA-UART-ALU FPGA-UART-ALU Public

   Forked from sifferman/verilog_template

   An FPGA ALU that can perform 32-bit addition, multiplication, and division over UART.

   SystemVerilog