soc: rtl87x2g: pm: add debug config and change stage time#203
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ZhiyuanTang17 wants to merge 1 commit intortkconnectivity:realtek-main-v3.5.0from
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soc: rtl87x2g: pm: add debug config and change stage time#203ZhiyuanTang17 wants to merge 1 commit intortkconnectivity:realtek-main-v3.5.0from
ZhiyuanTang17 wants to merge 1 commit intortkconnectivity:realtek-main-v3.5.0from
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ZhiyuanTang17
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Dec 25, 2025
ZhiyuanTang17
commented
- enlarge the exit and enter stage time
- add config to messure actual stage time
1. enlarge the exit and enter stage time 2. add config to messure actual stage time Signed-off-by: Zhiyuan Tang <zhiyuan_tang@realsil.com.cn>
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