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1 change: 1 addition & 0 deletions CHANGELOG.md
Original file line number Diff line number Diff line change
Expand Up @@ -10,6 +10,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/).
- Fix new `mismatched-lifetime-syntaxes` lint warnings
- Adapt RISC-V specific codegen for `riscv-peripheral` v0.3.0 rework
- Include `riscv-peripheral` peripherals in `Peripherals` struct
- `repr(transparent)` for field wrapper
- Ensure `__INTERRUPTS` are `#[no_mangle]` on Xtensa.
- Add `base_isa` field to `riscv_config` to allow the `riscv_rt::core_interrupt`
macro to properly generate start trap assembly routines in vectored mode.
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9 changes: 2 additions & 7 deletions src/generate/register.rs
Original file line number Diff line number Diff line change
Expand Up @@ -1497,12 +1497,6 @@ fn add_with_no_variants(
.as_ref()
.map(|feature| quote!(#[cfg_attr(feature = #feature, derive(defmt::Format))]));

let cast = if fty == "bool" {
quote! { val.0 as u8 != 0 }
} else {
quote! { val.0 as _ }
};

let desc = if let Some(rv) = reset_value {
format!("{desc}\n\nValue on reset: {rv}")
} else {
Expand All @@ -1513,11 +1507,12 @@ fn add_with_no_variants(
#[doc = #desc]
#defmt
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(transparent)]
pub struct #pc(#fty);
impl From<#pc> for #fty {
#[inline(always)]
fn from(val: #pc) -> Self {
#cast
val.0
}
}
});
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