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Kernel
The zero-GC, hardware cache-line-aligned storage backbone for AI cognitive memory.
The Spector Memory Kernel (spector-kernel) is the high-performance native storage engine powering Spector. Operating directly on off-heap memory via the Java 25 Foreign Function & Memory (FFM) API, the kernel delivers microsecond-level retrieval, high write concurrency, and strict multi-tenant data isolation.
Traditional AI databases store vector records on the JVM heap or delegate persistence to external network-attached databases. The Spector Memory Kernel takes a different approach: it manages structured off-heap byte buffers organized into memory-mapped bundles, eliminating garbage collection pauses and serialization overhead entirely.
graph TB
subgraph "External Ecosystem & Clients"
direction LR
PY["Python SDK<br/><i>spector-client</i>"]
TS["TypeScript SDK<br/><i>@spectrayan/spector-client</i>"]
JV["Java SDK<br/><i>com.spectrayan:spector-client</i>"]
REST["REST API & MCP<br/><i>port :7070</i>"]
end
subgraph "Application & Gateway Layer"
SYN["Spector Synapse Gateway<br/><i>Authentication, Routing, SSE Telemetry</i>"]
COG["Spector Memory Engine<br/><i>Cognitive Daemons, Cognitive Pathways, Scoring</i>"]
end
subgraph "Sealed Memory Kernel Boundary (Zero-GC Off-Heap)"
NK["NamespaceKernel Facade<br/><i>Thread-Safe Namespace Isolation</i>"]
subgraph "Memory Shape Abstractions"
RM["RecordMemory<br/><i>Contiguous Slots</i>"]
AM["AppendMemory<br/><i>Sequential Log</i>"]
GM["GraphMemory<br/><i>CSR Adjacency Slabs</i>"]
CM["ChainMemory<br/><i>Temporal Links</i>"]
HM["HashTableMemory<br/><i>Collision-Free Index</i>"]
YM["RegistryMemory<br/><i>Symbol Interning</i>"]
EM["EntityDirectoryMemory<br/><i>Entity & Role Indices</i>"]
IM["InsulaMemory<br/><i>Somatic Self-Model</i>"]
end
subgraph "Memory-Mapped Bundles"
RB["Runtime Bundle<br/><i>Hot working buffers, live graphs, & insula</i>"]
PB["Partition Bundles<br/><i>Episodic traces & semantic engrams</i>"]
IB["Identity Bundle<br/><i>Agent persona, soul, & compliance</i>"]
end
end
PY & TS & JV & REST --> SYN
SYN --> COG
COG --> NK
NK --> RM & AM & GM & CM & HM & YM & EM & IM
RM & AM & GM & CM & HM & YM & EM & IM --> RB & PB & IB
All cognitive memory records—including high-dimensional vector embeddings, associative graphs, 128-bit Bloom synaptic tags, and recall strength states—are held in off-heap memory segments. Because these buffers reside outside the managed JVM heap, the garbage collector never inspects, traces, or moves them, providing:
- Predictable Latency: Zero GC stop-the-world pauses, even under multi-gigabyte memory footprints.
- Cache-Line Alignment: Records are strictly aligned to 64-byte hardware cache lines, optimizing CPU prefetchers and memory bus saturation.
-
Direct OS Paging: Operating system page cache mechanisms handle paging and eviction transparently through memory-mapped I/O (
mmap).
The Memory Kernel maintains a strict architectural seal. Native memory segments, raw virtual addresses, and arena lifecycles are fully encapsulated within spector-kernel. Higher cognitive layers (spector-memory) interact solely through typed memory shapes and domain value objects. This design:
- Prevents unsafe memory access or off-heap memory leaks across upper subsystems.
- Guarantees thread-safe resource scoping across concurrent Virtual Threads.
- Allows the underlying storage layout to evolve without impacting client APIs.
Every stored engram cleanly decouples its immutable creation metadata from high-frequency mutable recall dynamics:
- Encoding Header (64 Bytes): Contains immutable properties recorded at memory formation (initial valence, arousal, base importance, timestamp, and 128-bit synaptic Bloom tags).
-
Strength State (96 Bytes): Resides in the dedicated Strength Region (
RegionId.STRENGTH). Tracks mutable access counters, long-term potentiation cooldowns, storage strength, and ACT-R recall timestamp history.
This complete physical separation prevents CPU cache-line false sharing during parallel multi-threaded scans, ensuring read-heavy search loops remain uninhibited by concurrent memory recall updates.
The agent's self-model sits in an identity.bundle, while the live runtime state mutates a separate InsulaMemory region in runtime.bundle. Spector separates persistent persona invariants from dynamic runtime state:
-
The Identity Plane (
identity.bundle): Houses the agent's persistent soul invariants, ethical axioms, compliance rules, and baseline salience weights outside volatile memory operations, requiring only a single lightweight file descriptor per identity hierarchy. -
The Somatic Self-Model (
InsulaMemory): Embedded withinruntime.bundle(RegionId.INSULA), this dedicated memory container tracks the agent's live, instantiated self-model—including dynamic confidence, task uncertainty, and affective homeostasis—as a versioned, CRC-32C validated state updated in sub-microsecond cycles during active reasoning.
Spector divides physical on-disk storage into two decoupled planes: the high-throughput Cognitive Memory Plane (namespaced data) and the long-term Identity Plane (accounts & tenants):
Every memory namespace (representing an individual user context, an agent conversation session, or a project workspace) receives its own dedicated off-heap bundle directory:
| Component | Path Pattern | Responsibility |
|---|---|---|
| Namespace Descriptor | namespaces/{xx}/{yy}/{id}/namespace.json |
Sizing configuration, vector dimensions, and tenant isolation metadata |
| Runtime Bundle | namespaces/{id}/runtime/runtime.bundle |
Hot working memory circular buffer, co-activation graph, entity registries, and dynamic self-model state (InsulaMemory) |
| Partition Bundles | namespaces/{id}/partitions/{seq}_{epoch}/partition.bundle |
Time-partitioned episodic chunks, long-term semantic engrams, procedural skills, and the 96-byte strength region |
| Write-Ahead Log | namespaces/{id}/wal/wal-000000.bin |
Crash-resilient chunked append-only mutation log with dual CRC-32 verification |
Identity bundles are decoupled from transient cognitive namespaces and housed under sharded account and tenant hierarchies:
| Component | Path Pattern | Responsibility |
|---|---|---|
| Account Identity Bundle | identity/accounts/{aa}/{bb}/{accountId}/identity.bundle |
End-user or AI agent identity (UserSoul or AgentSoul), custom salience profiles, and autobiographical continuity |
| Tenant Identity Bundle | identity/tenants/{tt}/{uu}/{tenantId}/identity.bundle |
Enterprise tenant identity (TenantSoul), compliance retention policies (POLICY), and organizational unit sub-souls (OrgUnitSoul in ORG_DIR) |
| Tenant Account Bundle | identity/tenants/.../accounts/.../identity.bundle |
Tenant-scoped account persona and overrides |
Explore the architectural components of the Spector Memory Kernel:
-
:material-package-variant-closed: Bundle Architecture
Learn how single-mmap bundle files organize memory regions with growable capacity and cache-line alignment.
-
:material-shape-outline: Memory Shapes
Discover the ten typed shape abstractions providing clean access patterns across all memory stores.
-
:material-binary: Binary Record Layouts
Examine the 64-byte pure encoding header, 128-bit Synaptic Bloom tags, and 96-byte strength state.
-
:material-shield-check-outline: WAL & Durability
Understand crash-resilient write-ahead logging, dual CRC-32 integrity verification, and recovery warming.
-
:material-map-marker-multiple-outline: Region Reference
Per-region binary layout documentation covering all 30 memory regions across Runtime, Partition, and Identity bundles.
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Architecture Decision Records (ADRs)
- Overview
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- Master Catalog (0001-0085)
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Memory Kernel & Storage Formats
- ADR-0001: Graph Compression Strategy for Entity Graph
- ADR-0002: Multi-Partition Recall Fan-Out & Frozen Reten...
- ADR-0003: Completing Hypergraph Entity-Graph Graduation
- ADR-0004: Mmap Bundle Architecture & File Descriptor Sc...
- ADR-0005: spector-memory Technical Debt Hardening
- ADR-0042: Graph Recall Architecture and Cognitive Trave...
- ADR-0043: Single-VMA Bundle Layout Specification
- ADR-0044: Memory Kernel Isolation, Composition, and Layout
- ADR-0045: Spector Memory Import & Export Pipeline
- ADR-0046: Single Engram, Four Stores Storage Architecture
- ADR-0047: Episodic Memory and Engram Model Hierarchy
- ADR-0057: Remediation of Hardcoded Memory Offsets and Alignment Constants
- ADR-0062: Spector Memory Organization — Three-Plane Architecture
- ADR-0082: Index Plane Lifecycle, Derived Views, and Reconciliation
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Active Inference Self-Model Engine (AISME)
- ADR-0006: Episodic Conversation Architecture
- ADR-0007: ReflectPathway — Biological Sleep Consolidation
- ADR-0008: Cognitive Substrate Evolution (TANGLE, GPM, M...
- ADR-0009: AISME Phase 1 — Homeostatic Affective Core
- ADR-0010: AISME Phase 2 — Free-Energy Guided Recall
- ADR-0011: AISME Phase 3 — Modern Hopfield Associative M...
- ADR-0012: AISME Phase 4 — Neural Manifold Distance (NMD)
- ADR-0013: AISME Phase 5 — Predictive Coding Narrative Self
- ADR-0014: AISME Phase 6 — Consciousness Continuity Metr...
- ADR-0015: AISME Phase 7 — Synaptic Relay Wiring & Pathw...
- ADR-0016: AISME Phase 8 — Closed-Loop Epistemic Learning
- ADR-0017: AISME Phase 9 — Generative Counterfactuals & ...
- ADR-0018: AISME Phase 10 — WanderPathway & Kernel Conti...
- ADR-0019: AISME Phase 11 — Expected Free Energy Policy ...
- ADR-0020: AISME Phase 12 — Continuous Self-Dynamics
- ADR-0023: AISME Complete Loop Closure & CognitiveVector...
- ADR-0024: Polymorphic SoulContext Hierarchy in AISME
- ADR-0027: Soul-Conditioned & Salience-Modulated Persona...
- ADR-0048: Cross-Capture Graph & CoActivation Kernel
- ADR-0049: Identity Trajectory Lyapunov Stability
- ADR-0050: Event Density Gating and Dynamic Epistemic Co...
- ADR-0051: Bayesian Online Change-Point Episode Segmenta...
- ADR-0052: Differential Privacy and Edge Anonymization
- ADR-0053: Multimodal Composite Importance Scoring
- ADR-0054: Lifespan-Adaptive Forgetting & Retention Kernel
- ADR-0055: LSR & RFF Dense Associative Memory Engineerin...
- ADR-0056: Log-Sum-ReLU (LSR) & Random Fourier Features ...
- ADR-0058: Linguistic & Vocal Prosody Expression Engine
- ADR-0063: Spacetime Vector Search and Synaptic Relay Architecture
- ADR-0064: Spacetime Simulation on Wander, Dream, and Express Pathways
- ADR-0071: Remember Cognitive Pathway Architecture
- ADR-0072: Six-Phase Fused Cognitive Scoring Pipeline
- ADR-0073: Recall Cognitive Pathway and Multi-Phase Retrieval Architecture
- ADR-0074: Reflect Cognitive Pathway and Sleep Consolidation Architecture
- ADR-0078: Salience Network and Thalamic Cognitive Profiles Architecture
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Platform, Synapse & Clustering
- ADR-0021: Nucleus Symmetric Hardware Abstraction Layer ...
- ADR-0022: Embodied Kinesics & Phenomenological MCP Engine
- ADR-0025: Declarative MCP Tool Definitions via JSON Sch...
- ADR-0026: Dual-Plane Concurrency & Async Queue Backpres...
- ADR-0028: Dual-Plane Memory Audit Architecture (Separat...
- ADR-0029: Episodic→Semantic Lineage Provenance Region
- ADR-0030: Unified Engram Encoding Header Architecture
- ADR-0031: Unified Configuration Architecture & Bypass E...
- ADR-0032: Persona Enactment — Soul as Policy over Memory
- ADR-0033: Decoupling Cognitive & Mathematical Kernels t...
- ADR-0034: Cell Topology, Namespace Ownership, and HA Cl...
- ADR-0035: Cognitive Pathway Framework Rearchitecture
- ADR-0036: Pathway Error Handling, Isolation, and Circui...
- ADR-0037: Ingestion Boundary and Sensory Relocation
- ADR-0038: SIMD-Accelerated BM25 Lexical Scoring Optimiz...
- ADR-0039: Robust Unified Rate Limiting Architecture
- ADR-0040: Universal Apache Camel Messaging Channels
- ADR-0041: Unified Connector Architecture for Ingestion
- ADR-0059: Java 27 Upgrade Strategy and Value Class Migration
- ADR-0060: Cognitive Continuity Layer and Decoded Mind Streams
- ADR-0061: In-Memory Multi-Tenant Quartz Scheduler
- ADR-0065: Client SDK Architecture, OpenAPI, and MCP Integration
- ADR-0066: Engine & CLI Stabilization — Issue #727 Hardening
- ADR-0067: Cell-Based High Availability and Namespace-Sticky Sharding
- ADR-0068: Phileas PII Redaction Engine for Spector Synapse
- ADR-0069: Synapse-Owned Tool Access Policy
- ADR-0070: Unified Error Taxonomy and Exception Handling Architecture
- ADR-0075: Extensible LLM and Multimodal Embedding Provider SPI
- ADR-0076: Zero-Dependency Pluggable Cache Abstraction
- ADR-0077: Model B Asynchronous Task Queue and Concurrency
- ADR-0079: Asynchronous Memory Event and Telemetry Notification Bus
- ADR-0080: Observed Memory and Pathway Metrics Telemetry Architecture
- ADR-0081: Dedicated Reactive Ingress and In-Process Path Router
- ADR-0083: Namespace-Isolated Memory Analytics & Telemetry
- ADR-0084: Dual-Plane Conversation Persistence
- ADR-0085: Dynamic Synapse Configuration Overrides and Runtime Propagation
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