feat(PCIE): PCIE Device Passthrough Refactoring #236
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Merge new features to main for hvisor-v0.1.2 release
…files (hvisor.bin), and improved startup speed
2.for loongarch, pCI can now access HT with the correct address header 3.correctly traverse the next bridge, which is a device with the next function 4.only function0 is checked to determine if it is a multifunction device
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I believe that PCI configuration log information should use hexadecimal format for easier manual debugging. For example: info!("begin enumerate {:#x?}", e);will be better than info!("begin enumerate {:#?}", e); |
| let _ = dev.write_bar(i as u8, value as u32); | ||
| i += 1; | ||
| bararr[i].set_virtual_value(value); | ||
| let _ = dev.write_bar(i as u8, (value >> 32) as u32); |
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If there is no allocator, we don't need to call dev.write_bar, because the value is already the same.
| let value = bararr[i].get_value64(); | ||
| bararr[i].set_virtual_value(value); | ||
| let _ = dev.write_bar(i as u8, value as u32); | ||
| i += 1; |
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For BARs with type PciMemType::High, their value now only stores high 32-bit instead of a complete u64, so we shall add something like let value = bararr[i].get_value64(); after i += 1.
| i += 1; | ||
| } | ||
| PciMemType::Io => { | ||
| writeln!(f, " IO @ 0x{:x}", bar.value)?; |
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Should change to
write!(f, "\n IO @ 0x{:x}", bar.value)?;| f, | ||
| "\n slot {} [mem 0x{:x}-0x{:x} 64bit", | ||
| i, | ||
| address, |
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Because bar.value now only stores low 32-bit in Mem64Low BAR, so we should read value of self.bararr[i+1] to calculate the complete u64 address.
| node.set_parent_bdf(parent_bdf); | ||
| self.next(match node.config_value.get_class().0 { | ||
| // class code 0x6 is bridge and class.1 0x0 is host bridge | ||
| 0x6 if node.config_value.get_class().1 != 0x0 => { |
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We shall use the specific class code (0x6, 0x4):
0x6 if node.config_value.get_class().1 == 0x4 => {Because there might be other bridges like ISA bridge (0x6, 0x1), that shall not be count as PCI bridge.
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1.Adjusted PCIe config format (magic version is 0x5). Please update hvisor-tool accordingly.
2.Added support for PCIe systems on x86/arm64/riscv/loongarch64 platforms.
3.Implemented three PCIe mechanisms: ECAM/DWC/loongarch64_pcie.
Fixes:
Fixes #209 (PCIe passthrough refactoring)
Fixes #234 (Resolved PCIe handler deadlock issue)
Fixes #228 (Deadlocks in hvisor)