boards: ace30: enable KCPS dynamic clock control #10368
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Enable dynamic clock switching for ACE30 Signed-off-by: Adrian Bonislawski <[email protected]>
abonislawski
requested review from
dbaluta,
kv2019i,
lbetlej,
lgirdwood,
mmaka1 and
plbossart
as code owners
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Pull Request Overview
This PR enables KCPS (Kilo Cycles Per Second) dynamic clock control for the Intel ADSP ACE30 PTL board configuration, allowing the system to dynamically adjust clock speeds at runtime.
Key Changes:
- Modified the ACE30 PTL board configuration to enable dynamic clock switching
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lgirdwood
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lgirdwood
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@abonislawski I assume default is max clock if any CPC in missing ?
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Yes, nothing has changed in this regard. I think we have most of the CPCs for PTL (but probably not all). |
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A lot of red on the PTL SDW CI, rerun CI again in case its a DUT issue. |
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SOFCI TEST |
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@abonislawski there is an IPC timeout, see https://sof-ci.01.org/sofpr/PR10368/build17444/devicetest/index.html?model=PTLP_RVP_SDW&testcase=check-playback-3rounds Could we have a wrong CPC somewhere ? |
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Enable dynamic clock switching for ACE30