A complete custom implementation of the 10GBASE-R Physical Layer (PHY) in VHDL. This implementation provides full control over the 10 Gigabit Ethernet physical layer without relying on encrypted vendor IP.
This project integrates the ALINX 10GbE UDP vendor design with a UART debug interface for monitoring network traffic and system status. It serves as the foundation for ITCH market data reception on the AX7325B (Kintex-7 XC7K325T) FPGA.
Implements multi-protocol market data parsing supporting NASDAQ (UDP/MoldUDP64), ASX (TCP/SoupBinTCP), and B3 Brazilian Exchange (UDP/SBE) market data feeds. Integrates with Project 33's 10GBASE-R PHY for 10GbE reception and outputs parsed messages via Aurora to FPGA2 (order book engine).
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