neorv32

🔑 Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.

📦 Prebuilt RISC-V GCC toolchains for x64 Linux.

♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.

📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.

Ada-language framework

✔️ Port of RISCOF to check NEORV32 for RISC-V ISA compatibility.

🐛 JTAG debug transport module (DTM) - compatible to the RISC-V debug specification.

NEORV32 RISC-V SoC running Zephyr RTOS on FPGA bare metal - with an extensible accelerator pipeline architecture, including an DMA-enabled programmable spectral filter pipeline - wrapped in C++20 HAL from fabric to std::span.

💾 FreeRTOS port for the NEORV32 RISC-V Processor.

Rust support for the open-source NEORV32 RISC-V microcontroller.

Core-NPU is an Open-source Wishbone NPU developed in VHDL to accelerate common ML operations by performing them in hardware

🐍 Port of MicroPython for the NEORV32 RISC-V Processor.

A XModem Bootloader for the NEORV32 CPU on the DE0-Nano board.

Cross-platform compatible firmware download tool for use with the NEORV32 bootloader, written in Python

RISC-V SoC on DE2-115: NEORV32 + 10 Wishbone peripherals + FreeRTOS + VGA/PS2/SDRAM + 22 CLI apps

NEORV32 port of the RISC-V Architectural Certification Tests (ACTs)

Dual SWD/JTAG CMSIS-DAP debug probe for RP2040 — supports ARM Cortex-M (SWD) and RISC-V (JTAG) from a board

Small Repository containing helpful material to develop programs for the NEORV32

NEORV32 and a generic FAT file system called FatFs.

Delivrables and code base from a CentraleSupéléc project