Laboratory workshop for ALINX AX309 development board (with FPGA Spartan 6)

Directly handles Xilinx bitstream files (native + compressed *.bit) instead of binaries (*.bin). Applies topspeed interface to FPGA.

A modified Caterina, fully respects 8 MHz clock and up to 500 mA board current draw.

A hardware-verified 8-bit Synchronous FIFO implemented on Xilinx Spartan-6 FPGA using Verilog HDL. Features robust signal debouncing, power-on reset logic, and real-time status monitoring.

FPGA-based Nintendo Entertainment System Emulator

Low-cost FPGA-based Bit Error Rate Tester and Eye Diagram Analyzer

Arm Cortex-M0 DesignStart SoC on Spartan-6 (Atlys): VHDL AHB-Lite peripherals, bare-metal firmware, verified testbenches, CI.

A hardware-verified 8-bit Synchronous FIFO implemented on Xilinx Spartan-6 FPGA using Verilog HDL. Features robust signal debouncing, power-on reset logic, and real-time status monitoring.

Simple LED counter for a Spartan 6 FPGA

FPGA DSP project: Spartan-6 DSP48A1 slice implemented in Verilog with directed testbenches. Includes QuestaSim simulation (DO file), Vivado elaboration/synthesis/implementation, timing/utilization/device views, and lint checks. Deliverables include waveforms, reports, and clean Messages tab (no critical warnings/errors).

Weather monitoring system using Verilog HDL