Rename some (wrong named) macro in samv71q-pinctrl.h for AFEC0 pins

[zebo9x]

The pin macro for SAM V71 Q relative to PE5 use as AFEC0 AD3 is now named PE5X_AFE0_AD3. Previously it was named as if it is relative to AFEC1 AD3 (PE5X_AFE1_AD3). A check can be made by reading the pinout table of ATSAMV71 for 144 pinout (datasheet: https://ww1.microchip.com/downloads/aemDocuments/documents/MCU32/ProductDocuments/DataSheets/SAM-E70-S70-V70-V71-Family-Data-Sheet-DS60001527.pdf) (start fo the table: page 28; relevant table section: page 33, LQFP pin 28).

[zebo9x]

note that I didn't change the comment above the macro definition

[zebo9x]

I think the changes for AD pins for AFEC0 / AFEC1 are done.

I have tested on the EVB of ATSAMV71Q21B (the sam_v71_xult board) by using a custom board folder with inside the devicetree (common and pinctrl).
In the code I'm using the property
/zephyr,user/io-channels = <&afec0, 0>, ...;
and the propery of pinctrl/.../pinmux is a list of all the pins.

[nandojve]

Hi @zebo9x ,

Yes, you are right. There is a typo in the pinconfig file:

hal_atmel/pinconfigs/sam-s70-e70-v7x.yml

Lines 802 to 815 in 56d60eb

	pe4:
	pincodes: [q]
	periph:
	- [a, ebi, d12, [j, n]]
	- [b, tc3, tiob10]
	extra:
	- [x, afe1, ad4]
	pe5:
	pincodes: [q]
	periph:
	- [a, ebi, d13, [j, n]]
	- [b, tc3, tclk10]
	extra:
	- [x, afe1, ad3]

You should fix in there and regenerate the files. There are documentation in the repo that explains how it works.
Make sure you follow the code guidelines when you write the commit, you should respect brief and comments max columns.

[nandojve]

Hi @zebo9x,

Is there any news from your side?

[zebo9x]

Sorry for the (very) late update. I will submit all the news on the code this weekend

[nandojve]

ping...

[zebo9x]

I have updated the pinconfigs of s70-e70-v7x and run the script to regenerate the proper include files. I have written a commit message acording to the guidelines. But I have commited to the master and not to the branch "patch-1". After this I have moved the commits into the correct branch. I'm sorry for the delay and thanks to the ping notifications.
Have a nice weekend.

[nandojve]

Hi @zebo9x ,

It is necessary a few changes:
1- All this changes should be on 1 commit.
2- You need respect the git brief and message max columns.
3- You need a PR in Zephyr mainline to bump the hal changes.

[ReggieMarr]

Is there any updates on when this might be reviewed/merged (or if I can assist)? I'm currently working on a project which requires this fix and currently am working off a patched version of this repo as a consequence.

[nandojve]

It is necessary a few changes:
1- All this changes should be on 1 commit.
2- You need respect the git brief and message max columns.
3- You need a PR in Zephyr mainline to bump the hal changes.

[zebo9x]

This weekend I'll have some time to rebase in one single commit and check if is all correct.

[nandojve]

Hi @zebo9x ,

Don't forget to apply as documented. See #41 as example.
Check, PR title, commits brief + descriptions, no merge commits etc.