ulp: get coprocessor reserved memory from dts

components/driver/gpio/include/driver/lp_io.h

@@ -0,0 +1,51 @@
+/*
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include "soc/soc_caps.h"
+#include "esp_err.h"
+#include "driver/gpio.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if SOC_LP_GPIO_MATRIX_SUPPORTED
+/**
+ * @brief Connect a RTC(LP) GPIO input with a peripheral signal, which tagged as input attribute
+ *
+ * @note There's no limitation on the number of signals that a RTC(LP) GPIO can connect with
+ *
+ * @param gpio_num GPIO number, especially, `LP_GPIO_MATRIX_CONST_ZERO_INPUT` means connect logic 0 to signal
+ *                                          `LP_GPIO_MATRIX_CONST_ONE_INPUT` means connect logic 1 to signal
+ * @param signal_idx LP peripheral signal index (tagged as input attribute)
+ * @param inv Whether the RTC(LP) GPIO input to be inverted or not
+ * @return
+ *      - ESP_OK Success
+ *      - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t lp_gpio_connect_in_signal(gpio_num_t gpio_num, uint32_t signal_idx, bool inv);
+
+/**
+ * @brief Connect a peripheral signal which tagged as output attribute with a RTC(LP) GPIO
+ *
+ * @note There's no limitation on the number of RTC(LP) GPIOs that a signal can connect with
+ *
+ * @param gpio_num GPIO number
+ * @param signal_idx LP peripheral signal index (tagged as input attribute), especially, `SIG_LP_GPIO_OUT_IDX` means disconnect RTC(LP) GPIO and other peripherals. Only the RTC GPIO driver can control the output level
+ * @param out_inv Whether to signal to be inverted or not
+ * @param out_en_inv Whether the output enable control is inverted or not
+ * @return
+ *      - ESP_OK Success
+ *      - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t lp_gpio_connect_out_signal(gpio_num_t gpio_num, uint32_t signal_idx, bool out_inv, bool out_en_inv);
+#endif // SOC_LP_GPIO_MATRIX_SUPPORTED
+
+#ifdef __cplusplus
+}
+#endif

components/driver/gpio/include/driver/rtc_io.h

@@ -198,6 +198,18 @@ esp_err_t rtc_gpio_set_drive_capability(gpio_num_t gpio_num, gpio_drive_cap_t st
  */
 esp_err_t rtc_gpio_get_drive_capability(gpio_num_t gpio_num, gpio_drive_cap_t* strength);
 
+/**
+ * @brief Select a RTC IOMUX function for the RTC IO
+ *
+ * @param gpio_num GPIO number
+ * @param func Function to assign to the pin
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t rtc_gpio_iomux_func_sel(gpio_num_t gpio_num, int func);
+
 #endif // SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
 
 #if SOC_RTCIO_HOLD_SUPPORTED

components/driver/gpio/rtc_io.c

@@ -145,6 +145,17 @@ esp_err_t rtc_gpio_pulldown_dis(gpio_num_t gpio_num)
     return ESP_OK;
 }
 
+#ifdef CONFIG_SOC_SERIES_ESP32C6
+esp_err_t rtc_gpio_iomux_func_sel(gpio_num_t gpio_num, int func)
+{
+    ESP_RETURN_ON_FALSE(rtc_gpio_is_valid_gpio(gpio_num), ESP_ERR_INVALID_ARG, RTCIO_TAG, "RTCIO number error");
+    RTCIO_ENTER_CRITICAL();
+    rtcio_hal_iomux_func_sel(rtc_io_number_get(gpio_num), func);
+    RTCIO_EXIT_CRITICAL();
+
+    return ESP_OK;
+}
+#endif
 #endif // SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
 
 #if SOC_RTCIO_HOLD_SUPPORTED

components/esp_hw_support/include/esp_private/periph_ctrl.h

@@ -11,6 +11,55 @@
 extern "C" {
 #endif
 
+/**
+ * @defgroup Reset and Clock Control APIs
+ * @{
+ */
+
+/**
+ * @brief Acquire the RCC lock for a peripheral module
+ *
+ * @note User code protected by this macro should be as short as possible, because it's a critical section
+ * @note This macro will increase the reference lock of that peripheral.
+ *       You can get the value before the increment from the `rc_name` local variable
+ */
+#define PERIPH_RCC_ACQUIRE_ATOMIC(rc_periph, rc_name)                \
+    for (uint8_t rc_name, _rc_cnt = 1, __DECLARE_RCC_RC_ATOMIC_ENV;     \
+         _rc_cnt ? (rc_name = periph_rcc_acquire_enter(rc_periph), 1) : 0; \
+         periph_rcc_acquire_exit(rc_periph, rc_name), _rc_cnt--)
+
+/**
+ * @brief Release the RCC lock for a peripheral module
+ *
+ * @note User code protected by this macro should be as short as possible, because it's a critical section
+ * @note This macro will decrease the reference lock of that peripheral.
+ *       You can get the value after the decrease from the `rc_name` local variable
+ */
+#define PERIPH_RCC_RELEASE_ATOMIC(rc_periph, rc_name)                \
+    for (uint8_t rc_name, _rc_cnt = 1, __DECLARE_RCC_RC_ATOMIC_ENV;     \
+         _rc_cnt ? (rc_name = periph_rcc_release_enter(rc_periph), 1) : 0; \
+         periph_rcc_release_exit(rc_periph, rc_name), _rc_cnt--)
+
+/**
+ * @brief A simplified version of `PERIPH_RCC_ACQUIRE/RELEASE_ATOMIC`, without a reference count
+ *
+ * @note User code protected by this macro should be as short as possible, because it's a critical section
+ */
+#define PERIPH_RCC_ATOMIC()                   \
+    for (int _rc_cnt = 1, __DECLARE_RCC_ATOMIC_ENV; \
+         _rc_cnt ? (periph_rcc_enter(), 1) : 0;     \
+         periph_rcc_exit(), _rc_cnt--)
+
+/** @cond */
+// The following functions are not intended to be used directly by the developers
+uint8_t periph_rcc_acquire_enter(periph_module_t periph);
+void periph_rcc_acquire_exit(periph_module_t periph, uint8_t ref_count);
+uint8_t periph_rcc_release_enter(periph_module_t periph);
+void periph_rcc_release_exit(periph_module_t periph, uint8_t ref_count);
+void periph_rcc_enter(void);
+void periph_rcc_exit(void);
+/** @endcond */
+
 /**
  * @brief Enable peripheral module by un-gating the clock and de-asserting the reset signal.
  *

components/esp_hw_support/include/esp_private/uart_share_hw_ctrl.h

@@ -0,0 +1,36 @@
+
+/*
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include "soc/soc_caps.h"
+#include "esp_private/periph_ctrl.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if SOC_PERIPH_CLK_CTRL_SHARED
+#define HP_UART_SRC_CLK_ATOMIC()       PERIPH_RCC_ATOMIC()
+#else
+#define HP_UART_SRC_CLK_ATOMIC()
+#endif
+
+#if SOC_RCC_IS_INDEPENDENT
+#define HP_UART_BUS_CLK_ATOMIC()
+#else
+#define HP_UART_BUS_CLK_ATOMIC()       PERIPH_RCC_ATOMIC()
+#endif
+
+#if (SOC_UART_LP_NUM >= 1)
+#define LP_UART_SRC_CLK_ATOMIC()    PERIPH_RCC_ATOMIC()
+#define LP_UART_BUS_CLK_ATOMIC()    PERIPH_RCC_ATOMIC()
+#endif
+
+#ifdef __cplusplus
+}
+#endif

components/esp_hw_support/periph_ctrl.c

@@ -21,6 +21,40 @@ static int periph_spinlock;
 
 static uint8_t ref_counts[PERIPH_MODULE_MAX] = {0};
 
+IRAM_ATTR void periph_rcc_enter(void)
+{
+    ENTER_CRITICAL_SECTION();
+}
+
+IRAM_ATTR void periph_rcc_exit(void)
+{
+    LEAVE_CRITICAL_SECTION();
+}
+
+IRAM_ATTR uint8_t periph_rcc_acquire_enter(periph_module_t periph)
+{
+    periph_rcc_enter();
+    return ref_counts[periph];
+}
+
+IRAM_ATTR void periph_rcc_acquire_exit(periph_module_t periph, uint8_t ref_count)
+{
+    ref_counts[periph] = ++ref_count;
+    periph_rcc_exit();
+}
+
+IRAM_ATTR uint8_t periph_rcc_release_enter(periph_module_t periph)
+{
+    periph_rcc_enter();
+    return ref_counts[periph] - 1;
+}
+
+IRAM_ATTR void periph_rcc_release_exit(periph_module_t periph, uint8_t ref_count)
+{
+    ref_counts[periph] = ref_count;
+    periph_rcc_exit();
+}
+
 void periph_module_enable(periph_module_t periph)
 {
     assert(periph < PERIPH_MODULE_MAX);

components/esp_hw_support/port/esp32c6/rtc_clk.c

@@ -364,7 +364,9 @@ rtc_xtal_freq_t rtc_clk_xtal_freq_get(void)
 {
     uint32_t xtal_freq_mhz = clk_ll_xtal_load_freq_mhz();
     if (xtal_freq_mhz == 0) {
+#if !defined(CONFIG_SOC_ESP32C6_LPCORE)
         ESP_HW_LOGW(TAG, "invalid RTC_XTAL_FREQ_REG value, assume 40MHz");
+#endif
         clk_ll_xtal_store_freq_mhz(RTC_XTAL_FREQ_40M);
         return RTC_XTAL_FREQ_40M;
     }

components/hal/esp32c6/clk_tree_hal.c

@@ -10,7 +10,9 @@
 #include "hal/assert.h"
 #include "hal/log.h"
 
+#if !defined(CONFIG_SOC_ESP32C6_LPCORE)
 static const char *CLK_HAL_TAG = "clk_hal";
+#endif
 
 uint32_t clk_hal_soc_root_get_freq_mhz(soc_cpu_clk_src_t cpu_clk_src)
 {
@@ -69,7 +71,9 @@ uint32_t clk_hal_xtal_get_freq_mhz(void)
 {
     uint32_t freq = clk_ll_xtal_load_freq_mhz();
     if (freq == 0) {
+#if !defined(CONFIG_SOC_ESP32C6_LPCORE)
         HAL_LOGW(CLK_HAL_TAG, "invalid RTC_XTAL_FREQ_REG value, assume 40MHz");
+#endif
         return (uint32_t)RTC_XTAL_FREQ_40M;
     }
     return freq;