soc: imx93: enable imx93 video pll

Added video_pll instance to soc dtsi.

Signed-off-by: Ruoshan Shi <[email protected]>

Author: RuoshanShi

boards/shields/waveshare_dsi_lcd/boards/frdm_imx93_mimx9352_a55.overlay

@@ -59,3 +59,14 @@
 &dsi_panel {
 	mipi-dsi = <&mipi_dsi>;
 };
+
+&video_pll {
+	compatible = "nxp,imx93-video-pll";
+	rdiv = <1>;
+	mfi = <200>;
+	mfn = <0>;
+	mfd = <1>;
+	odiv = <12>;
+	pll-frequency = <400000000>;
+	status = "okay";
+};

drivers/display/Kconfig.mcux_lcdifv3

@@ -7,7 +7,6 @@ menuconfig DISPLAY_MCUX_LCDIFV3
 	default y
 	depends on DT_HAS_NXP_IMX_LCDIFV3_ENABLED
 	depends on CLOCK_CONTROL
-	select INIT_VIDEO_PLL
 	help
 	  Enable support for mcux LCDIFV3 driver.
 

dts/arm/nxp/nxp_imx93_m33.dtsi

@@ -175,6 +175,12 @@
 			#io-channel-cells = <1>;
 			clocks = <&ccm IMX_CCM_SAR_ADC1_CLK 0x0 0>;
 		};
+
+		video_pll: videopll@44481400 {
+			compatible = "nxp,imx93-video-pll";
+			reg = <0x44481400 0x1000>;
+			status = "disabled";
+		};
 	};
 };
 

dts/arm64/nxp/nxp_mimx93_a55.dtsi

@@ -116,6 +116,12 @@
 		status = "disabled";
 	};
 
+	video_pll: videopll@44481400 {
+		compatible = "nxp,imx93-video-pll";
+		reg = <0x44481400 0x1000>;
+		status = "disabled";
+	};
+
 	wdog3: watchdog@42490000 {
 		compatible = "nxp,wdog32";
 		reg = <0x42490000 0x1000>;

soc/nxp/imx/imx9/imx93/CMakeLists.txt

@@ -7,7 +7,6 @@ if(CONFIG_SOC_MIMX9352_A55)
   zephyr_sources_ifdef(CONFIG_ARM_MMU a55/mmu_regions.c)
 
   zephyr_sources(common_clock_set.c)
-  zephyr_sources(a55/soc.c)
   set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm64/scripts/linker.ld CACHE INTERNAL "")
 elseif(CONFIG_SOC_MIMX9352_M33)
   zephyr_include_directories(.)

soc/nxp/imx/imx9/imx93/Kconfig

@@ -26,9 +26,6 @@ config MCUX_CORE_SUFFIX
 	default "_ca55" if SOC_MIMX9352_A55
 	default "_cm33" if SOC_MIMX9352_M33
 
-config INIT_VIDEO_PLL
-	bool "Init Video PLL"
-
 if SOC_MIMX9352_M33
 
 config TRDC_MCUX_TRDC_1