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drivers: mbox: Add mailbox driver for SOPHGO CVI series
This implements a mailbox driver for CV18xx, a series of multi-core SoCs by SOPHGO. This driver enables the little core of CV18xx running RTOS to communicate with its big core running Linux. Signed-off-by: honglin leng <[email protected]> Signed-off-by: Chen Xingyu <[email protected]>
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‎drivers/mbox/CMakeLists.txt‎

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@@ -22,3 +22,4 @@ zephyr_library_sources_ifdef(CONFIG_MBOX_IVSHMEM mbox_ivshmem.c)
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zephyr_library_sources_ifdef(CONFIG_MBOX_TI_OMAP_MAILBOX mbox_ti_omap.c)
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zephyr_library_sources_ifdef(CONFIG_MBOX_RENESAS_RZ_MHU mbox_renesas_rz_mhu.c)
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zephyr_library_sources_ifdef(CONFIG_MBOX_MHUV3 mbox_mhuv3.c)
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zephyr_library_sources_ifdef(CONFIG_MBOX_SOPHGO_CVI mbox_sophgo_cvi.c)

‎drivers/mbox/Kconfig‎

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@@ -26,6 +26,7 @@ source "drivers/mbox/Kconfig.ivshmem"
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source "drivers/mbox/Kconfig.ti_omap"
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source "drivers/mbox/Kconfig.renesas_rz"
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source "drivers/mbox/Kconfig.mhuv3"
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source "drivers/mbox/Kconfig.sophgo"
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config MBOX_INIT_PRIORITY

‎drivers/mbox/Kconfig.sophgo‎

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# Copyright (c) 2024 honglin leng <[email protected]>
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# SPDX-License-Identifier: Apache-2.0
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config MBOX_SOPHGO_CVI
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bool "SOPHGO CVI series Mailbox controller"
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default y
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depends on DT_HAS_SOPHGO_CVI_MAILBOX_ENABLED
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help
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Enable driver for the SOPHGO CVI series Mailbox.

‎drivers/mbox/mbox_sophgo_cvi.c‎

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/*
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* Copyright (c) 2024 honglin leng <[email protected]>
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/drivers/mbox.h>
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#include <zephyr/irq.h>
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#include <string.h>
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#define DT_DRV_COMPAT sophgo_cvi_mailbox
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#define MBOX_BASE DT_INST_REG_ADDR(0)
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#define MBOX_TX_CPU DT_INST_PROP(0, tx_cpu)
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#define MBOX_RX_CPU DT_INST_PROP(0, rx_cpu)
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#define MBOX_INT_ENABLE(cpu) (MBOX_BASE + 0x00 + (0x04 * cpu))
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#define MBOX_INT_CLEAR(cpu) (MBOX_BASE + 0x10 + (0x10 * cpu))
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#define MBOX_INT_DONE(cpu) (MBOX_BASE + 0x18 + (0x10 * cpu))
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#define MBOX_INT_TRIGER (MBOX_BASE + 0x60)
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#define MBOX_BUFFER (MBOX_BASE + 0x400)
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#define MBOX_MAX_NUM 8
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struct mbox_cvi_data {
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mbox_callback_t cb[MBOX_MAX_NUM];
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void *user_data[MBOX_MAX_NUM];
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};
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static struct mbox_cvi_data mbox_data;
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static void mbox_isr(const struct device *dev)
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{
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ARG_UNUSED(dev);
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uint8_t set_val;
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uint8_t valid_val;
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uint8_t tmp_valid_val;
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struct mbox_msg msg;
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set_val = sys_read8(MBOX_INT_DONE(MBOX_RX_CPU));
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if (set_val) {
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for (int i = 0; i < MBOX_MAX_NUM; i++) {
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valid_val = set_val & BIT(i);
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if (valid_val) {
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msg.data = (const unsigned long *)MBOX_BUFFER + i;
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sys_write8(valid_val, MBOX_INT_CLEAR(MBOX_RX_CPU));
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tmp_valid_val = sys_read8(MBOX_INT_ENABLE(MBOX_RX_CPU));
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tmp_valid_val &= ~valid_val;
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sys_write8(tmp_valid_val, MBOX_INT_ENABLE(MBOX_RX_CPU));
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if (mbox_data.cb[i] != NULL) {
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mbox_data.cb[i](dev, i, mbox_data.user_data[i], &msg);
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*(unsigned long *)msg.data = 0x0;
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}
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}
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}
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}
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}
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static int mbox_cvi_send(const struct device *dev, uint32_t channel, const struct mbox_msg *msg)
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{
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uint8_t tmp_mbox_info;
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ARG_UNUSED(dev);
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memcpy((unsigned long *)MBOX_BUFFER + channel, msg->data, msg->size);
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sys_write8(BIT(channel), MBOX_INT_CLEAR(MBOX_TX_CPU));
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tmp_mbox_info = sys_read8(MBOX_INT_ENABLE(MBOX_TX_CPU));
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tmp_mbox_info |= BIT(channel);
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sys_write8(tmp_mbox_info, MBOX_INT_ENABLE(MBOX_TX_CPU));
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sys_write8(BIT(channel), MBOX_INT_TRIGER);
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return 0;
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}
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static int mbox_cvi_register_callback(const struct device *dev, uint32_t channel,
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mbox_callback_t cb, void *user_data)
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{
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ARG_UNUSED(dev);
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if (channel >= MBOX_MAX_NUM) {
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return -EINVAL;
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}
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mbox_data.cb[channel] = cb;
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mbox_data.user_data[channel] = user_data;
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return 0;
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}
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static int mbox_cvi_mtu_get(const struct device *dev)
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{
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ARG_UNUSED(dev);
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/* We only support signalling */
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return 0;
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}
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static uint32_t mbox_cvi_max_channels_get(const struct device *dev)
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{
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ARG_UNUSED(dev);
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return MBOX_MAX_NUM;
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}
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static int mbox_cvi_set_enabled(const struct device *dev, uint32_t channel, bool enable)
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{
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ARG_UNUSED(dev);
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ARG_UNUSED(channel);
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ARG_UNUSED(enable);
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return 0;
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}
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static int mbox_cvi_init(const struct device *dev)
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{
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ARG_UNUSED(dev);
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IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority), mbox_isr, DEVICE_DT_INST_GET(0), 0);
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irq_enable(DT_INST_IRQN(0));
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return 0;
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}
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static DEVICE_API(mbox, mbox_cvi_driver_api) = {
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.send = mbox_cvi_send,
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.register_callback = mbox_cvi_register_callback,
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.mtu_get = mbox_cvi_mtu_get,
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.max_channels_get = mbox_cvi_max_channels_get,
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.set_enabled = mbox_cvi_set_enabled,
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};
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DEVICE_DT_INST_DEFINE(0, mbox_cvi_init, NULL, NULL, NULL, POST_KERNEL, CONFIG_MBOX_INIT_PRIORITY,
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&mbox_cvi_driver_api);

‎dts/bindings/mbox/sophgo,cvi-mailbox.yaml‎

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# Copyright (c) 2024 honglin leng <[email protected]>
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# SPDX-License-Identifier: Apache-2.0
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description: SOPHGO CVI series Mailbox controller
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compatible: "sophgo,cvi-mailbox"
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include: [base.yaml, mailbox-controller.yaml]
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properties:
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reg:
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required: true
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interrupts:
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required: true
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channel-max:
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type: int
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required: true
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description: Supported channels max
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rx-cpu:
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type: int
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enum: [1, 2, 3, 4]
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description: |
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Receiver CPU Index.
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tx-cpu:
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type: int
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enum: [1, 2, 3, 4]
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description: |
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Sender CPU Index.The CVI platform has a total of 4 CPUs, each with its own
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mailbox.
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The mailbox controller can be used to send messages between CPUs.
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mbox-cells:
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- channel

‎dts/riscv/sophgo/cv180x.dtsi‎

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soc {
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compatible = "sophgo,cv180x", "simple-bus";
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mbox: mailbox@1900000 {
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compatible = "sophgo,cvi-mailbox";
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reg = <0x1900000 DT_SIZE_K(4)>;
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interrupts = <61 1>;
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channel-max = <8>;
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tx-cpu = <1>;
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rx-cpu = <2>;
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#mbox-cells = <1>;
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status = "disabled";
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};
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pinctrl: pin-controller@3001000 {
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compatible = "sophgo,cvi-pinctrl";
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reg = <0x3001000 DT_SIZE_K(4)>;

‎dts/riscv/sophgo/cv181x.dtsi‎

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soc {
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compatible = "sophgo,cv181x", "simple-bus";
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mbox: mailbox@1900000 {
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compatible = "sophgo,cvi-mailbox";
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reg = <0x1900000 DT_SIZE_K(4)>;
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interrupts = <61 1>;
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channel-max = <8>;
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tx-cpu = <1>;
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rx-cpu = <2>;
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#mbox-cells = <1>;
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status = "disabled";
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};
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pinctrl: pin-controller@3001000 {
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compatible = "sophgo,cvi-pinctrl";
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reg = <0x3001000 DT_SIZE_K(4)>;

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